[llvm] [GISEL][RISCV] RegBank Scalable Vector Load/Store (PR #99932)

[Jiahan Xie via llvm-commits]

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@@ -355,10 +355,20 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
   switch (Opc) {
   case TargetOpcode::G_LOAD: {
     LLT Ty = MRI.getType(MI.getOperand(0).getReg());
-    OpdsMapping[0] = GPRValueMapping;
-    OpdsMapping[1] = GPRValueMapping;
+    TypeSize Size = Ty.getSizeInBits();
+    if (Ty.isVector()) {
+      OpdsMapping[0] = getVRBValueMapping(Size.getKnownMinValue());
+      OpdsMapping[1] = getVRBValueMapping(Size.getKnownMinValue());
+    } else if (isPreISelGenericFloatingPointOpcode(Opc)) {
+      OpdsMapping[0] = getFPValueMapping(Size.getFixedValue());
+      OpdsMapping[1] = getFPValueMapping(Size.getFixedValue());
+    } else {
+      OpdsMapping[0] = GPRValueMapping;
+      OpdsMapping[1] = GPRValueMapping;
+    }
     // Use FPR64 for s64 loads on rv32.
-    if (GPRSize == 32 && Ty.getSizeInBits() == 64) {
+    if (GPRSize == 32 && Ty.getSizeInBits().getKnownMinValue() == 64 &&
+        !Ty.isVector()) {
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jiahanxie353 wrote:

not confident about this `if` statement

https://github.com/llvm/llvm-project/pull/99932