[llvm] [AArch64] Optimize two large shifts and a combine into a single combine and shift (PR #99480)

[via llvm-commits]

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``````````bash
git-clang-format --diff b7a6cca218aef4e18ce03a58561555ef0dee7231 c5176e19524d92e3009a32798e10e766f9104cfd --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index d2db216984..2cbfc93c20 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -19163,8 +19163,7 @@ static SDValue performConcatVectorsCombine(SDNode *N,
     //     ushr    v0.8h, v0.8h, #4
     //
     // This optimization reduces instruction count.
-    if (N00Opc == AArch64ISD::VLSHR &&
-        N10Opc == AArch64ISD::VLSHR &&
+    if (N00Opc == AArch64ISD::VLSHR && N10Opc == AArch64ISD::VLSHR &&
         N00->getOperand(1) == N10->getOperand(1)) {
 
       SDValue N000 = N00->getOperand(0);
@@ -19173,8 +19172,7 @@ static SDValue performConcatVectorsCombine(SDNode *N,
                N101ConstVal = N10->getConstantOperandVal(1),
                NScalarSize = N->getValueType(0).getScalarSizeInBits();
 
-      if (N001ConstVal == N101ConstVal &&
-          N001ConstVal > NScalarSize) {
+      if (N001ConstVal == N101ConstVal && N001ConstVal > NScalarSize) {
 
         SDValue Uzp = DAG.getNode(AArch64ISD::UZP2, dl, VT, N000, N100);
         SDValue NewShiftConstant =

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https://github.com/llvm/llvm-project/pull/99480