[llvm] [GISel][TableGen] Generate getRegBankFromRegClass (PR #99896)

[Matt Arsenault via llvm-commits]

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+/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
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arsenm wrote:

This is just a generated output, it's not a test. The test needs to be the tablegen input checking the generated output 

https://github.com/llvm/llvm-project/pull/99896