[llvm] [GISel][TableGen] Generate getRegBankFromRegClass (PR #99896)

[Kai Nacke via llvm-commits]

redstar wrote:

> Does this improve compile time at all? I assume this can't deal with the AMDGPU ambiguous i1 case?

I have not yet check the compile time. My main interest is to generate more code from the TableGen defintion. Well, I now have a Mac since a week, so I should now be able to measure the compile time impact....

The AMDGPU i1 case is indeed not handled. I found no reliable way to handle this exception. AArch64 and PowerPC also need some special handling because of register classes which could be mapped to several register banks. One way to solve the latter problem could be to add more information to TableGen, but I made no effort in this direction so far. 

https://github.com/llvm/llvm-project/pull/99896