[llvm] Add more cases for computeOverflowForSignedAdd (PR #99900)

via llvm-commits llvm-commits at lists.llvm.org
Mon Jul 22 10:03:09 PDT 2024


https://github.com/AtariDreams created https://github.com/llvm/llvm-project/pull/99900

https://godbolt.org/z/jczPzqa6e Even with fwrapv, IR knows this does not wrap

>From 4072ffa1aee863e6614a8eab2804b2d8dbfc17c9 Mon Sep 17 00:00:00 2001
From: Rose <gfunni234 at gmail.com>
Date: Mon, 22 Jul 2024 12:39:08 -0400
Subject: [PATCH] Add more cases for computeOverflowForSignedAdd

https://godbolt.org/z/jczPzqa6e Even with fwrapv, IR knows this does not wrap
---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 02d44cd36ae53..9cec62a3be613 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -4241,9 +4241,20 @@ SelectionDAG::computeOverflowForSignedAdd(SDValue N0, SDValue N1) const {
   // cannot overflow.
   if (ComputeNumSignBits(N0) > 1 && ComputeNumSignBits(N1) > 1)
     return OFK_Never;
+  
+    // smulhi + any value never overflow
+  KnownBits N1Known = computeKnownBits(N1);
+  if (N0.getOpcode() == ISD::SMUL_LOHI && N0.getResNo() == 1)
+    return OFK_Never;
 
-  // TODO: Add ConstantRange::signedAddMayOverflow handling.
-  return OFK_Sometime;
+  KnownBits N0Known = computeKnownBits(N0);
+  if (N1.getOpcode() == ISD::SMUL_LOHI && N1.getResNo() == 1)
+    return OFK_Never;
+  
+    // Fallback to ConstantRange::signedAddMayOverflow handling.
+  ConstantRange N0Range = ConstantRange::fromKnownBits(N0Known, false);
+  ConstantRange N1Range = ConstantRange::fromKnownBits(N1Known, false);
+  return mapOverflowResult(N0Range.signedAddMayOverflow(N1Range));
 }
 
 SelectionDAG::OverflowKind



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