[clang] [llvm] [PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (PR #99511)
David Tenty via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 22 08:10:14 PDT 2024
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@@ -3485,9 +3485,11 @@ unsigned PPCInstrInfo::getSpillTarget() const {
// With P10, we may need to spill paired vector registers or accumulator
// registers. MMA implies paired vectors, so we can just check that.
bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
- return Subtarget.isISAFuture() ? 3 : IsP10Variant ?
- 2 : Subtarget.hasP9Vector() ?
- 1 : 0;
+ // P11 uses the P10 target.
+ return Subtarget.isISAFuture() ? 4
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daltenty wrote:
This doesn't quite make sense to me, we extended the length of the array but we don't cover all elements. We should probably just leave this as is and make sure `IsP10Variant` is true for pwr11.
If I understand right, our additional lit run lines already added (e.g. [mma-acc-spill.ll](https://github.com/llvm/llvm-project/commit/37c4ac8545537077788d4e00be7473fe0e2113c3#diff-563c38a308e920559647a63033a141ada8b6e1332c51310ce5fbcc40df8121c3, etc.) should do that.
https://github.com/llvm/llvm-project/pull/99511
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