[clang] [llvm] [RISCV][FMV] Support target_clones (PR #85786)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 22 04:22:56 PDT 2024
https://github.com/BeMg updated https://github.com/llvm/llvm-project/pull/85786
>From 19e6ccf34e3c1e5a3bd0152da0f5a7915203eb57 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Mon, 10 Jun 2024 22:22:42 -0700
Subject: [PATCH 01/25] [RISCV][FMV] Support target_clones
---
.../clang/Basic/DiagnosticFrontendKinds.td | 4 +
clang/include/clang/Basic/TargetInfo.h | 3 +-
clang/lib/AST/ASTContext.cpp | 12 +
clang/lib/CodeGen/CGBuiltin.cpp | 78 +++++++
clang/lib/CodeGen/CodeGenFunction.cpp | 91 +++++++-
clang/lib/CodeGen/CodeGenFunction.h | 7 +
clang/lib/CodeGen/CodeGenModule.cpp | 5 +-
clang/lib/CodeGen/Targets/RISCV.cpp | 23 ++
clang/lib/Sema/SemaDeclAttr.cpp | 26 +++
.../attr-target-clones-riscv-invaild.c | 8 +
clang/test/CodeGen/attr-target-clones-riscv.c | 205 ++++++++++++++++++
.../CodeGenCXX/attr-target-clones-riscv.cpp | 204 +++++++++++++++++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 32 +++
.../llvm/TargetParser/RISCVTargetParser.h | 4 +
llvm/lib/TargetParser/RISCVTargetParser.cpp | 25 +++
15 files changed, 724 insertions(+), 3 deletions(-)
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv-invaild.c
create mode 100644 clang/test/CodeGen/attr-target-clones-riscv.c
create mode 100644 clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
create mode 100644 clang/test/SemaCXX/attr-target-clones-riscv.cpp
diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
index 12a4617c64d87..b2b63674ecc07 100644
--- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td
+++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td
@@ -375,4 +375,8 @@ def warn_missing_symbol_graph_dir : Warning<
def err_ast_action_on_llvm_ir : Error<
"cannot apply AST actions to LLVM IR file '%0'">,
DefaultFatal;
+
+def err_os_unsupport_riscv_target_clones : Error<
+ "target_clones is currently only supported on Linux">;
+
}
diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h
index a58fb5f979272..f31d88a354ea2 100644
--- a/clang/include/clang/Basic/TargetInfo.h
+++ b/clang/include/clang/Basic/TargetInfo.h
@@ -1496,7 +1496,8 @@ class TargetInfo : public TransferrableTargetInfo,
/// Identify whether this target supports multiversioning of functions,
/// which requires support for cpu_supports and cpu_is functionality.
bool supportsMultiVersioning() const {
- return getTriple().isX86() || getTriple().isAArch64();
+ return getTriple().isX86() || getTriple().isAArch64() ||
+ getTriple().isRISCV();
}
/// Identify whether this target supports IFuncs.
diff --git a/clang/lib/AST/ASTContext.cpp b/clang/lib/AST/ASTContext.cpp
index 90bcbea072e39..e493872e14c36 100644
--- a/clang/lib/AST/ASTContext.cpp
+++ b/clang/lib/AST/ASTContext.cpp
@@ -14127,6 +14127,18 @@ void ASTContext::getFunctionFeatureMap(llvm::StringMap<bool> &FeatureMap,
Target->getTargetOpts().FeaturesAsWritten.begin(),
Target->getTargetOpts().FeaturesAsWritten.end());
Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
+ } else if (Target->getTriple().isRISCV()) {
+ StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
+ std::vector<std::string> Features;
+ if (VersionStr != "default") {
+ ParsedTargetAttr ParsedAttr = Target->parseTargetAttr(VersionStr);
+ Features.insert(Features.begin(), ParsedAttr.Features.begin(),
+ ParsedAttr.Features.end());
+ }
+ Features.insert(Features.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.begin(),
+ Target->getTargetOpts().FeaturesAsWritten.end());
+ Target->initFeatureMap(FeatureMap, getDiagnostics(), TargetCPU, Features);
} else {
std::vector<std::string> Features;
StringRef VersionStr = TC->getFeatureStr(GD.getMultiVersionIndex());
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 5639239359ab8..8e522ed9a87f8 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -62,6 +62,7 @@
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/ScopedPrinter.h"
#include "llvm/TargetParser/AArch64TargetParser.h"
+#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/TargetParser/X86TargetParser.h"
#include <optional>
#include <sstream>
@@ -14308,6 +14309,16 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
return Builder.CreateCall(Func);
}
+Value *CodeGenFunction::EmitRISCVCpuInit() {
+ llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
+ llvm::FunctionCallee Func =
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bit");
+ cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true);
+ cast<llvm::GlobalValue>(Func.getCallee())
+ ->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
+ return Builder.CreateCall(Func);
+}
+
Value *CodeGenFunction::EmitX86CpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy,
/*Variadic*/ false);
@@ -14360,6 +14371,73 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef<StringRef> FeaturesStrs) {
return Result;
}
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
+ unsigned &MaxGroupIDUsed) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+ CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true);
+
+ auto LoadFeatureBit = [&](unsigned Index) {
+ // Create GEP then load.
+ Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
+ std::vector<llvm::Value *> GEPIndices = {llvm::ConstantInt::get(Int32Ty, 0),
+ llvm::ConstantInt::get(Int32Ty, 1),
+ IndexVal};
+ Value *Ptr =
+ Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+ Value *FeaturesBit =
+ Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
+ return FeaturesBit;
+ };
+
+ SmallVector<unsigned long long> RequireFeatureBits =
+ llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs);
+ Value *Result = Builder.getTrue();
+ for (unsigned i = 0; i < RequireFeatureBits.size(); i++) {
+ if (!RequireFeatureBits[i])
+ continue;
+ MaxGroupIDUsed = i;
+ Value *Mask = Builder.getInt64(RequireFeatureBits[i]);
+ Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask);
+ Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
+ Result = Builder.CreateAnd(Result, Cmp);
+ }
+
+ return Result;
+}
+
+Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
+
+ const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+ llvm::ArrayType *ArrayOfInt64Ty =
+ llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
+ llvm::Constant *RISCVFeaturesBits =
+ CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true);
+
+ auto LoadMaxGroupID = [&]() {
+ std::vector<llvm::Value *> GEPIndices = {
+ llvm::ConstantInt::get(Int32Ty, 0), llvm::ConstantInt::get(Int32Ty, 0)};
+ llvm::Value *Ptr =
+ Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+ Value *Length =
+ Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
+ return Length;
+ };
+
+ Value *UsedMaxGroupID = Builder.getInt64(MaxGroupIDUsed);
+ Value *GroupIDResult =
+ Builder.CreateICmpULT(UsedMaxGroupID, LoadMaxGroupID());
+
+ return GroupIDResult;
+}
+
Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
const CallExpr *E) {
if (BuiltinID == Builtin::BI__builtin_cpu_is)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 1e98bea8c8ce3..f2b05caded05e 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2863,10 +2863,99 @@ void CodeGenFunction::EmitMultiVersionResolver(
case llvm::Triple::aarch64:
EmitAArch64MultiVersionResolver(Resolver, Options);
return;
+ case llvm::Triple::riscv32:
+ case llvm::Triple::riscv64:
+ EmitRISCVMultiVersionResolver(Resolver, Options);
+ return;
default:
- assert(false && "Only implemented for x86 and AArch64 targets");
+ assert(false && "Only implemented for x86, AArch64 and RISC-V targets");
+ }
+}
+
+void CodeGenFunction::EmitRISCVMultiVersionResolver(
+ llvm::Function *Resolver, ArrayRef<MultiVersionResolverOption> Options) {
+
+ if (getContext().getTargetInfo().getTriple().getOS() !=
+ llvm::Triple::OSType::Linux) {
+ CGM.getDiags().Report(diag::err_os_unsupport_riscv_target_clones);
+ return;
+ }
+
+ llvm::BasicBlock *CurBlock = createBasicBlock("resolver_entry", Resolver);
+ Builder.SetInsertPoint(CurBlock);
+ EmitRISCVCpuInit();
+
+ bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
+ bool HasDefault = false;
+ int DefaultIndex = 0;
+ // Check the each candidate function.
+ for (unsigned Index = 0; Index < Options.size(); Index++) {
+
+ if (Options[Index].Conditions.Features[0].starts_with("default")) {
+ HasDefault = true;
+ DefaultIndex = Index;
+ continue;
+ }
+
+ Builder.SetInsertPoint(CurBlock);
+
+ std::vector<std::string> TargetAttrFeats =
+ getContext()
+ .getTargetInfo()
+ .parseTargetAttr(Options[Index].Conditions.Features[0])
+ .Features;
+
+ if (!TargetAttrFeats.empty()) {
+
+ llvm::BasicBlock *SecondCond =
+ createBasicBlock("resovler_cond", Resolver);
+
+ Builder.SetInsertPoint(SecondCond);
+ unsigned MaxGroupIDUsed = 0;
+ llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
+
+ for (auto Feat: TargetAttrFeats)
+ CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
+
+ llvm::Value *SecondCondition =
+ EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
+
+ Builder.SetInsertPoint(CurBlock);
+ llvm::Value *FirstCondition = EmitRISCVFeatureBitsLength(MaxGroupIDUsed);
+
+ llvm::BasicBlock *RetBlock =
+ createBasicBlock("resolver_return", Resolver);
+ CGBuilderTy RetBuilder(*this, RetBlock);
+ CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder,
+ Options[Index].Function, SupportsIFunc);
+ llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver);
+
+ Builder.SetInsertPoint(CurBlock);
+ Builder.CreateCondBr(FirstCondition, SecondCond, ElseBlock);
+
+ Builder.SetInsertPoint(SecondCond);
+ Builder.CreateCondBr(SecondCondition, RetBlock, ElseBlock);
+
+ CurBlock = ElseBlock;
+ }
}
+
+ // Finally, emit the default one.
+ if (HasDefault) {
+ Builder.SetInsertPoint(CurBlock);
+ CreateMultiVersionResolverReturn(
+ CGM, Resolver, Builder, Options[DefaultIndex].Function, SupportsIFunc);
+ return;
+ }
+
+ // If no generic/default, emit an unreachable.
+ Builder.SetInsertPoint(CurBlock);
+ llvm::CallInst *TrapCall = EmitTrapCall(llvm::Intrinsic::trap);
+ TrapCall->setDoesNotReturn();
+ TrapCall->setDoesNotThrow();
+ Builder.CreateUnreachable();
+ Builder.ClearInsertionPoint();
}
void CodeGenFunction::EmitAArch64MultiVersionResolver(
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index eebb865e8f42c..1f0d7c5d1c980 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -5314,6 +5314,9 @@ class CodeGenFunction : public CodeGenTypeCache {
void
EmitAArch64MultiVersionResolver(llvm::Function *Resolver,
ArrayRef<MultiVersionResolverOption> Options);
+ void
+ EmitRISCVMultiVersionResolver(llvm::Function *Resolver,
+ ArrayRef<MultiVersionResolverOption> Options);
private:
QualType getVarArgType(const Expr *Arg);
@@ -5338,6 +5341,10 @@ class CodeGenFunction : public CodeGenTypeCache {
FormAArch64ResolverCondition(const MultiVersionResolverOption &RO);
llvm::Value *EmitAArch64CpuSupports(const CallExpr *E);
llvm::Value *EmitAArch64CpuSupports(ArrayRef<StringRef> FeatureStrs);
+ llvm::Value *EmitRISCVCpuInit();
+ llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeatureStrs,
+ unsigned &MaxGroupIDUsed);
+ llvm::Value *EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed);
};
inline DominatingLLVMValue::saved_type
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp
index 71192cb0e8c4a..e5ebcf5596ab0 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -4249,7 +4249,10 @@ void CodeGenModule::emitMultiVersionFunctions() {
Feats.clear();
if (getTarget().getTriple().isAArch64())
TC->getFeatures(Feats, I);
- else {
+ else if (getTarget().getTriple().isRISCV()) {
+ StringRef Version = TC->getFeatureStr(I);
+ Feats.push_back(Version);
+ } else {
StringRef Version = TC->getFeatureStr(I);
if (Version.starts_with("arch="))
Architecture = Version.drop_front(sizeof("arch=") - 1);
diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index f2add9351c03c..ba81bf7d1dd0a 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -63,9 +63,32 @@ class RISCVABIInfo : public DefaultABIInfo {
CharUnits Field2Off) const;
ABIArgInfo coerceVLSVector(QualType Ty) const;
+
+ using ABIInfo::appendAttributeMangling;
+ void appendAttributeMangling(TargetClonesAttr *Attr, unsigned Index,
+ raw_ostream &Out) const override;
+ void appendAttributeMangling(StringRef AttrStr,
+ raw_ostream &Out) const override;
};
} // end anonymous namespace
+void RISCVABIInfo::appendAttributeMangling(TargetClonesAttr *Attr,
+ unsigned Index,
+ raw_ostream &Out) const {
+ appendAttributeMangling(Attr->getFeatureStr(Index), Out);
+}
+
+void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr,
+ raw_ostream &Out) const {
+ if (AttrStr == "default") {
+ Out << ".default";
+ return;
+ }
+
+ Out << '.';
+ Out << AttrStr;
+}
+
void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
QualType RetTy = FI.getReturnType();
if (!getCXXABI().classifyReturnType(FI))
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 5fd8622c90dd8..33336272f1254 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -3127,6 +3127,32 @@ bool Sema::checkTargetClonesAttrString(
/*IncludeLocallyStreaming=*/false))
return Diag(LiteralLoc,
diag::err_sme_streaming_cannot_be_multiversioned);
+ } else if (TInfo.getTriple().isRISCV()) {
+ // Suppress warn_target_clone_mixed_values
+ HasCommas = false;
+
+ // Only support arch=+ext,... syntax.
+ if (Str.starts_with("arch=+")) {
+ // parseTargetAttr will parse full version string,
+ // the following split Cur string is no longer interesting.
+ if ((!Cur.starts_with("arch=")))
+ continue;
+
+ ParsedTargetAttr TargetAttr =
+ Context.getTargetInfo().parseTargetAttr(Str);
+ if (TargetAttr.Features.empty())
+ return Diag(CurLoc, diag::warn_unsupported_target_attribute)
+ << Unsupported << None << Str << TargetClones;
+ } else if (Str == "default") {
+ DefaultIsDupe = HasDefault;
+ HasDefault = true;
+ } else {
+ return Diag(CurLoc, diag::warn_unsupported_target_attribute)
+ << Unsupported << None << Str << TargetClones;
+ }
+ if (llvm::is_contained(StringsBuffer, Str) || DefaultIsDupe)
+ Diag(CurLoc, diag::warn_target_clone_duplicate_options);
+ StringsBuffer.push_back(Str);
} else {
// Other targets ( currently X86 )
if (Cur.starts_with("arch=")) {
diff --git a/clang/test/CodeGen/attr-target-clones-riscv-invaild.c b/clang/test/CodeGen/attr-target-clones-riscv-invaild.c
new file mode 100644
index 0000000000000..f5e8f40d7a8f3
--- /dev/null
+++ b/clang/test/CodeGen/attr-target-clones-riscv-invaild.c
@@ -0,0 +1,8 @@
+// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
+
+// CHECK-UNSUPPORT-OS: error: target_clones is currently only supported on Linux
+__attribute__((target_clones("default", "arch=+c"))) int foo2(void) {
+ return 2;
+}
+
+int bar() { return foo1()+foo2(); }
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
new file mode 100644
index 0000000000000..1088dd56a4d83
--- /dev/null
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -0,0 +1,205 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -target-feature +i -emit-llvm -o - %s | FileCheck %s
+
+__attribute__((target_clones("default", "arch=+m"))) int foo1(void) {
+ return 1;
+}
+__attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; }
+__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; }
+__attribute__((target_clones("default", "arch=+zbb,+v"))) int
+foo4(void) {
+ return 4;
+}
+__attribute__((target_clones("default"))) int foo5(void) { return 5; }
+__attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; }
+
+int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
+
+//.
+// CHECK: @__riscv_feature_bits = external dso_local global { i32, [1 x i64] }
+// CHECK: @foo1.ifunc = weak_odr alias i32 (), ptr @foo1
+// CHECK: @foo2.ifunc = weak_odr alias i32 (), ptr @foo2
+// CHECK: @foo3.ifunc = weak_odr alias i32 (), ptr @foo3
+// CHECK: @foo4.ifunc = weak_odr alias i32 (), ptr @foo4
+// CHECK: @foo5.ifunc = weak_odr alias i32 (), ptr @foo5
+// CHECK: @foo6.ifunc = weak_odr alias i32 (), ptr @foo6
+// CHECK: @foo1 = weak_odr ifunc i32 (), ptr @foo1.resolver
+// CHECK: @foo2 = weak_odr ifunc i32 (), ptr @foo2.resolver
+// CHECK: @foo3 = weak_odr ifunc i32 (), ptr @foo3.resolver
+// CHECK: @foo4 = weak_odr ifunc i32 (), ptr @foo4.resolver
+// CHECK: @foo5 = weak_odr ifunc i32 (), ptr @foo5.resolver
+// CHECK: @foo6 = weak_odr ifunc i32 (), ptr @foo6.resolver
+//.
+// CHECK-LABEL: define dso_local signext i32 @foo1.default(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 1
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"foo1.arch=+m"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @foo1.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo2.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"foo2.arch=+zbb"
+// CHECK: resolver_else:
+// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 0, [[TMP6]]
+// CHECK-NEXT: br i1 [[TMP7]], label [[RESOVLER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
+// CHECK: resovler_cond1:
+// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096
+// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096
+// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
+// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]]
+// CHECK: resolver_return2:
+// CHECK-NEXT: ret ptr @"foo2.arch=+m"
+// CHECK: resolver_else3:
+// CHECK-NEXT: ret ptr @foo2.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo3.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 3
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"foo3.arch=+zbb,+c"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @foo3.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo4.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 4
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"foo4.arch=+zbb,+v"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @foo4.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo5.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 5
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: ret ptr @foo5.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo6.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
+// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"foo6.arch=+zvkt"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @foo6.default
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @bar(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[CALL:%.*]] = call signext i32 @foo1()
+// CHECK-NEXT: [[CALL1:%.*]] = call signext i32 @foo2()
+// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
+// CHECK-NEXT: [[CALL2:%.*]] = call signext i32 @foo3()
+// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
+// CHECK-NEXT: [[CALL4:%.*]] = call signext i32 @foo4()
+// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
+// CHECK-NEXT: [[CALL6:%.*]] = call signext i32 @foo5()
+// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
+// CHECK-NEXT: ret i32 [[ADD7]]
+//
+//.
+// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
+// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
+// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" }
+// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb" }
+// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zbb,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zvkt" }
+//.
+// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
+// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
+// CHECK: [[META3]] = !{!"rv64i2p1"}
+// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
+// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
+//.
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
new file mode 100644
index 0000000000000..73bbfcd8b9652
--- /dev/null
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -0,0 +1,204 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+// RUN: %clang_cc1 -std=c++11 -triple riscv64-linux-gnu -target-feature +i -target-feature +m -emit-llvm %s -o - | FileCheck %s
+
+__attribute__((target_clones("default", "arch=+m"))) int foo1(void) {
+ return 1;
+}
+__attribute__((target_clones("default", "arch=+zbb", "arch=+m"))) int foo2(void) { return 2; }
+__attribute__((target_clones("default", "arch=+zbb,+c"))) int foo3(void) { return 3; }
+__attribute__((target_clones("default", "arch=+zbb,+v"))) int
+foo4(void) {
+ return 4;
+}
+__attribute__((target_clones("default"))) int foo5(void) { return 5; }
+__attribute__((target_clones("default", "arch=+zvkt"))) int foo6(void) { return 2; }
+
+int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
+
+//.
+// CHECK: @__riscv_feature_bits = external dso_local global { i32, [1 x i64] }
+// CHECK: @_Z4foo1v.ifunc = weak_odr alias i32 (), ptr @_Z4foo1v
+// CHECK: @_Z4foo2v.ifunc = weak_odr alias i32 (), ptr @_Z4foo2v
+// CHECK: @_Z4foo3v.ifunc = weak_odr alias i32 (), ptr @_Z4foo3v
+// CHECK: @_Z4foo4v.ifunc = weak_odr alias i32 (), ptr @_Z4foo4v
+// CHECK: @_Z4foo5v.ifunc = weak_odr alias i32 (), ptr @_Z4foo5v
+// CHECK: @_Z4foo6v.ifunc = weak_odr alias i32 (), ptr @_Z4foo6v
+// CHECK: @_Z4foo1v = weak_odr ifunc i32 (), ptr @_Z4foo1v.resolver
+// CHECK: @_Z4foo2v = weak_odr ifunc i32 (), ptr @_Z4foo2v.resolver
+// CHECK: @_Z4foo3v = weak_odr ifunc i32 (), ptr @_Z4foo3v.resolver
+// CHECK: @_Z4foo4v = weak_odr ifunc i32 (), ptr @_Z4foo4v.resolver
+// CHECK: @_Z4foo5v = weak_odr ifunc i32 (), ptr @_Z4foo5v.resolver
+// CHECK: @_Z4foo6v = weak_odr ifunc i32 (), ptr @_Z4foo6v.resolver
+//.
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v.default(
+// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 1
+//
+//
+// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"_Z4foo1v.arch=+m"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @_Z4foo1v.default
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
+// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+zbb"
+// CHECK: resolver_else:
+// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 0, [[TMP6]]
+// CHECK-NEXT: br i1 [[TMP7]], label [[RESOVLER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
+// CHECK: resovler_cond1:
+// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096
+// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096
+// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
+// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]]
+// CHECK: resolver_return2:
+// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+m"
+// CHECK: resolver_else3:
+// CHECK-NEXT: ret ptr @_Z4foo2v.default
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 3
+//
+//
+// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"_Z4foo3v.arch=+zbb,+c"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @_Z4foo3v.default
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 4
+//
+//
+// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"_Z4foo4v.arch=+zbb,+v"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @_Z4foo4v.default
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo5v.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 5
+//
+//
+// CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: ret ptr @_Z4foo5v.default
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v.default(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
+// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
+// CHECK-NEXT: resolver_entry:
+// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488
+// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
+// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK: resolver_return:
+// CHECK-NEXT: ret ptr @"_Z4foo6v.arch=+zvkt"
+// CHECK: resolver_else:
+// CHECK-NEXT: ret ptr @_Z4foo6v.default
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z3barv(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z4foo1v()
+// CHECK-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_Z4foo2v()
+// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]]
+// CHECK-NEXT: [[CALL2:%.*]] = call noundef signext i32 @_Z4foo3v()
+// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]]
+// CHECK-NEXT: [[CALL4:%.*]] = call noundef signext i32 @_Z4foo4v()
+// CHECK-NEXT: [[ADD5:%.*]] = add nsw i32 [[ADD3]], [[CALL4]]
+// CHECK-NEXT: [[CALL6:%.*]] = call noundef signext i32 @_Z4foo5v()
+// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[ADD5]], [[CALL6]]
+// CHECK-NEXT: ret i32 [[ADD7]]
+//
+//.
+// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
+// CHECK: attributes #[[ATTR1:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }
+// CHECK: attributes #[[ATTR2:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" }
+// CHECK: attributes #[[ATTR3:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #[[ATTR4:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" }
+//.
+// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
+// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
+// CHECK: [[META2:![0-9]+]] = !{i32 6, !"riscv-isa", [[META3:![0-9]+]]}
+// CHECK: [[META3]] = !{!"rv64i2p1_m2p0_zmmul1p0"}
+// CHECK: [[META4:![0-9]+]] = !{i32 8, !"SmallDataLimit", i32 0}
+// CHECK: [[META5:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"}
+//.
diff --git a/clang/test/SemaCXX/attr-target-clones-riscv.cpp b/clang/test/SemaCXX/attr-target-clones-riscv.cpp
new file mode 100644
index 0000000000000..edee5f7c231e9
--- /dev/null
+++ b/clang/test/SemaCXX/attr-target-clones-riscv.cpp
@@ -0,0 +1,32 @@
+// RUN: %clang_cc1 -triple riscv64-linux-gnu -fsyntax-only -verify -fexceptions -fcxx-exceptions %s -std=c++14
+
+// expected-warning at +1 {{unsupported 'mcpu=sifive-u74' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
+void __attribute__((target_clones("default", "mcpu=sifive-u74"))) mcpu() {}
+
+// expected-warning at +1 {{unsupported 'mtune=sifive-u74' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
+void __attribute__((target_clones("default", "mtune=sifive-u74"))) mtune() {}
+
+// expected-warning at +1 {{version list contains duplicate entries}}
+void __attribute__((target_clones("default", "arch=+c", "arch=+c"))) dupVersion() {}
+
+// expected-warning at +1 {{unsupported '' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
+void __attribute__((target_clones("default", ""))) emptyVersion() {}
+
+// expected-error at +1 {{'target_clones' multiversioning requires a default target}}
+void __attribute__((target_clones("arch=+c"))) withoutDefault() {}
+
+// expected-warning at +1 {{unsupported '+c' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
+void __attribute__((target_clones("default", "+c"))) invaildVersion() {}
+
+// expected-warning at +1 {{unsupported 'arch=rv64g' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
+void __attribute__((target_clones("default", "arch=rv64g"))) fullArchString() {}
+
+
+void lambda() {
+ // expected-error at +1 {{attribute 'target_clones' multiversioned functions do not yet support lambdas}}
+ auto x = []() __attribute__((target_clones("default"))){};
+ x();
+ // expected-error at +1 {{attribute 'target_clones' multiversioned functions do not yet support lambdas}}
+ auto y = []() __attribute__((target_clones("arch=+v", "default"))){};
+ y();
+}
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index c75778952e0f5..f12ded9170c93 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -32,6 +32,8 @@ struct RISCVExtensionBitmask {
};
} // namespace RISCVExtensionBitmaskTable
+static constexpr unsigned RISCVFeatureBitSize = 1;
+
// We use 64 bits as the known part in the scalable vector types.
static constexpr unsigned RVVBitsPerBlock = 64;
@@ -45,6 +47,8 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool hasFastScalarUnalignedAccess(StringRef CPU);
bool hasFastVectorUnalignedAccess(StringRef CPU);
+llvm::SmallVector<unsigned long long>
+ getRequireFeatureBitMask(ArrayRef<StringRef>);
} // namespace RISCV
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 49a35bfcf4b9b..b2f8ee344d414 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -144,6 +144,31 @@ struct LessExtName {
};
} // namespace
+static Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask>
+getExtensionBitmask(StringRef ExtName) {
+ ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
+ RISCVExtensionBitmaskTable::ExtensionBitmask;
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
+
+ if (I != ExtBitmasks.end())
+ return *I;
+
+ return createStringError("Unsupport extension");
+}
+
+llvm::SmallVector<unsigned long long>
+getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
+ llvm::SmallVector<unsigned long long> BitMasks(RISCV::RISCVFeatureBitSize);
+
+ for (auto Ext : Exts) {
+ Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmask =
+ getExtensionBitmask(Ext);
+ assert(ExtBitmask && "This extension doesn't has bitmask.");
+ BitMasks[ExtBitmask->GroupID] |= (1ULL << ExtBitmask->BitPosition);
+ }
+
+ return BitMasks;
+}
} // namespace RISCV
namespace RISCVVType {
>From df9b5a6f6b2d23a046c659a94bb5bee4a71fcc3f Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Fri, 12 Jul 2024 02:17:34 -0700
Subject: [PATCH 02/25] Fixup format
---
clang/lib/CodeGen/CodeGenFunction.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index f2b05caded05e..ed37b2a12809c 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2915,9 +2915,9 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
unsigned MaxGroupIDUsed = 0;
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
- for (auto Feat: TargetAttrFeats)
+ for (auto Feat : TargetAttrFeats)
CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
-
+
llvm::Value *SecondCondition =
EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
>From 87d8fd079bc62420cf71d8f1810687ad2b1b19e2 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jul 2024 06:15:27 -0700
Subject: [PATCH 03/25] __init_riscv_features_bit -> __init_riscv_features_bits
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/test/CodeGen/attr-target-clones-riscv.c | 12 ++++++------
clang/test/CodeGenCXX/attr-target-clones-riscv.cpp | 12 ++++++------
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 8e522ed9a87f8..5e851d519e0b1 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14312,7 +14312,7 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
Value *CodeGenFunction::EmitRISCVCpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
llvm::FunctionCallee Func =
- CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bit");
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bits");
cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true);
cast<llvm::GlobalValue>(Func.getCallee())
->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index 1088dd56a4d83..38adba7eac312 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: ret ptr @foo5.default
//
//
@@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index 73bbfcd8b9652..024c1c715c617 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: ret ptr @_Z4foo5v.default
//
//
@@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bit()
+// CHECK-NEXT: call void @__init_riscv_features_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
>From 2306cdb13eeb6c3856b67e6c2189ec347a9277fd Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jul 2024 19:06:17 -0700
Subject: [PATCH 04/25] Update __init_riscv_feature_bits naming
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/test/CodeGen/attr-target-clones-riscv.c | 12 ++++++------
clang/test/CodeGenCXX/attr-target-clones-riscv.cpp | 12 ++++++------
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 5e851d519e0b1..74e42a39af0c9 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14312,7 +14312,7 @@ Value *CodeGenFunction::EmitAArch64CpuInit() {
Value *CodeGenFunction::EmitRISCVCpuInit() {
llvm::FunctionType *FTy = llvm::FunctionType::get(VoidTy, false);
llvm::FunctionCallee Func =
- CGM.CreateRuntimeFunction(FTy, "__init_riscv_features_bits");
+ CGM.CreateRuntimeFunction(FTy, "__init_riscv_feature_bits");
cast<llvm::GlobalValue>(Func.getCallee())->setDSOLocal(true);
cast<llvm::GlobalValue>(Func.getCallee())
->setDLLStorageClass(llvm::GlobalValue::DefaultStorageClass);
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index 38adba7eac312..27e8d20f7ba17 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo5.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: ret ptr @foo5.default
//
//
@@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index 024c1c715c617..6bac679cf1425 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -38,7 +38,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -62,7 +62,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -98,7 +98,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -122,7 +122,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
@@ -146,7 +146,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo5v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: ret ptr @_Z4foo5v.default
//
//
@@ -158,7 +158,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
-// CHECK-NEXT: call void @__init_riscv_features_bits()
+// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
>From 7c95873f6fce36eccd97f4026ce3bbed6884a73d Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jul 2024 23:11:38 -0700
Subject: [PATCH 05/25] Rename variable
---
clang/lib/CodeGen/CodeGenFunction.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index ed37b2a12809c..e10223037d642 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2918,7 +2918,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
for (auto Feat : TargetAttrFeats)
CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
- llvm::Value *SecondCondition =
+ llvm::Value *FeatsCondition =
EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
Builder.SetInsertPoint(CurBlock);
@@ -2935,7 +2935,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
Builder.CreateCondBr(FirstCondition, SecondCond, ElseBlock);
Builder.SetInsertPoint(SecondCond);
- Builder.CreateCondBr(SecondCondition, RetBlock, ElseBlock);
+ Builder.CreateCondBr(FeatsCondition, RetBlock, ElseBlock);
CurBlock = ElseBlock;
}
>From a1d868727252a35f8d97e1fd9cdd32b375b34b0e Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jul 2024 23:17:05 -0700
Subject: [PATCH 06/25] SecondCond -> FeatsCondBB
---
clang/lib/CodeGen/CodeGenFunction.cpp | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index e10223037d642..f0ca53cd9fcd9 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2907,17 +2907,16 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
.Features;
if (!TargetAttrFeats.empty()) {
-
- llvm::BasicBlock *SecondCond =
- createBasicBlock("resovler_cond", Resolver);
-
- Builder.SetInsertPoint(SecondCond);
unsigned MaxGroupIDUsed = 0;
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
for (auto Feat : TargetAttrFeats)
CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
+ llvm::BasicBlock *FeatsCondBB =
+ createBasicBlock("resovler_cond", Resolver);
+
+ Builder.SetInsertPoint(FeatsCondBB);
llvm::Value *FeatsCondition =
EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
@@ -2932,9 +2931,9 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver);
Builder.SetInsertPoint(CurBlock);
- Builder.CreateCondBr(FirstCondition, SecondCond, ElseBlock);
+ Builder.CreateCondBr(FirstCondition, FeatsCondBB, ElseBlock);
- Builder.SetInsertPoint(SecondCond);
+ Builder.SetInsertPoint(FeatsCondBB);
Builder.CreateCondBr(FeatsCondition, RetBlock, ElseBlock);
CurBlock = ElseBlock;
>From aac07632dead64fab6d6ad084ade674535ee9eec Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jul 2024 23:44:28 -0700
Subject: [PATCH 07/25] Add comment
---
clang/lib/CodeGen/CodeGenFunction.cpp | 28 +++++++++++++++++++++++++--
1 file changed, 26 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index f0ca53cd9fcd9..f1b6c7394a5d1 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2906,6 +2906,29 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
.parseTargetAttr(Options[Index].Conditions.Features[0])
.Features;
+ // Two conditions need to be checked for the current version:
+ //
+ // 1. LengthCondition: The maximum group ID of the required extension
+ // does not exceed the runtime object's length.
+ // __riscv_feature_bits.length > MAX_USED_GROUPID
+ //
+ // 2. FeaturesCondition: The bitmask of the required extension has been
+ // enabled by the runtime object.
+ // (__riscv_feature_bits.features[i] & REQUIRED_BITMASK) ==
+ // REQUIRED_BITMASK
+ //
+ // When both conditions are met, return this version of the function.
+ // Otherwise, try the next version.
+ //
+ // if (LengthConditionVersion1 && FeaturesConditionVersion1)
+ // return Version1;
+ // else if (LengthConditionVersion2 && FeaturesConditionVersion2)
+ // return Version2;
+ // else if (LengthConditionVersion3 && FeaturesConditionVersion3)
+ // return Version3;
+ // ...
+ // else
+ // return DefaultVersion;
if (!TargetAttrFeats.empty()) {
unsigned MaxGroupIDUsed = 0;
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
@@ -2921,7 +2944,8 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
Builder.SetInsertPoint(CurBlock);
- llvm::Value *FirstCondition = EmitRISCVFeatureBitsLength(MaxGroupIDUsed);
+ llvm::Value *MaxGroupLengthCondition =
+ EmitRISCVFeatureBitsLength(MaxGroupIDUsed);
llvm::BasicBlock *RetBlock =
createBasicBlock("resolver_return", Resolver);
@@ -2931,7 +2955,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver);
Builder.SetInsertPoint(CurBlock);
- Builder.CreateCondBr(FirstCondition, FeatsCondBB, ElseBlock);
+ Builder.CreateCondBr(MaxGroupLengthCondition, FeatsCondBB, ElseBlock);
Builder.SetInsertPoint(FeatsCondBB);
Builder.CreateCondBr(FeatsCondition, RetBlock, ElseBlock);
>From ed8b21155576ca435ad896364f16f1565a9dcf35 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Tue, 16 Jul 2024 23:46:23 -0700
Subject: [PATCH 08/25] Move MaxGroupIDUsed closer to use
---
clang/lib/CodeGen/CodeGenFunction.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index f1b6c7394a5d1..2c880eafb8f1e 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2930,7 +2930,6 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
// else
// return DefaultVersion;
if (!TargetAttrFeats.empty()) {
- unsigned MaxGroupIDUsed = 0;
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
for (auto Feat : TargetAttrFeats)
@@ -2940,6 +2939,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
createBasicBlock("resovler_cond", Resolver);
Builder.SetInsertPoint(FeatsCondBB);
+ unsigned MaxGroupIDUsed = 0;
llvm::Value *FeatsCondition =
EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
>From 3241b1569fccbf48e4ae4e20b32bb7bfc70df979 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 18:58:34 -0700
Subject: [PATCH 09/25] invaild -> invalid
---
...-clones-riscv-invaild.c => attr-target-clones-riscv-invalid.c} | 0
1 file changed, 0 insertions(+), 0 deletions(-)
rename clang/test/CodeGen/{attr-target-clones-riscv-invaild.c => attr-target-clones-riscv-invalid.c} (100%)
diff --git a/clang/test/CodeGen/attr-target-clones-riscv-invaild.c b/clang/test/CodeGen/attr-target-clones-riscv-invalid.c
similarity index 100%
rename from clang/test/CodeGen/attr-target-clones-riscv-invaild.c
rename to clang/test/CodeGen/attr-target-clones-riscv-invalid.c
>From d1e41bf70a704f0257e7854ade7d45797ee00a09 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 19:12:01 -0700
Subject: [PATCH 10/25] unsigned long long -> uint64
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
llvm/include/llvm/TargetParser/RISCVTargetParser.h | 3 +--
llvm/lib/TargetParser/RISCVTargetParser.cpp | 5 ++---
3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 74e42a39af0c9..9c435df81aa41 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14395,7 +14395,7 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
return FeaturesBit;
};
- SmallVector<unsigned long long> RequireFeatureBits =
+ SmallVector<uint64_t> RequireFeatureBits =
llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs);
Value *Result = Builder.getTrue();
for (unsigned i = 0; i < RequireFeatureBits.size(); i++) {
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index f12ded9170c93..7346d25957ce8 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -47,8 +47,7 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool hasFastScalarUnalignedAccess(StringRef CPU);
bool hasFastVectorUnalignedAccess(StringRef CPU);
-llvm::SmallVector<unsigned long long>
- getRequireFeatureBitMask(ArrayRef<StringRef>);
+llvm::SmallVector<uint64_t> getRequireFeatureBitMask(ArrayRef<StringRef>);
} // namespace RISCV
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index b2f8ee344d414..56e4bd209d868 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -156,9 +156,8 @@ getExtensionBitmask(StringRef ExtName) {
return createStringError("Unsupport extension");
}
-llvm::SmallVector<unsigned long long>
-getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
- llvm::SmallVector<unsigned long long> BitMasks(RISCV::RISCVFeatureBitSize);
+llvm::SmallVector<uint64_t> getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
+ llvm::SmallVector<uint64_t> BitMasks(RISCV::RISCVFeatureBitSize);
for (auto Ext : Exts) {
Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmask =
>From edf70274b7ac0a77affa0f7ebf6e1f8cbc9b85e6 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 19:17:12 -0700
Subject: [PATCH 11/25] Update GEPIndices
---
clang/lib/CodeGen/CGBuiltin.cpp | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 9c435df81aa41..ca69e76cbcfcd 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14385,9 +14385,8 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
auto LoadFeatureBit = [&](unsigned Index) {
// Create GEP then load.
Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
- std::vector<llvm::Value *> GEPIndices = {llvm::ConstantInt::get(Int32Ty, 0),
- llvm::ConstantInt::get(Int32Ty, 1),
- IndexVal};
+ llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
+ IndexVal};
Value *Ptr =
Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
Value *FeaturesBit =
@@ -14422,8 +14421,7 @@ Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true);
auto LoadMaxGroupID = [&]() {
- std::vector<llvm::Value *> GEPIndices = {
- llvm::ConstantInt::get(Int32Ty, 0), llvm::ConstantInt::get(Int32Ty, 0)};
+ llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(0)};
llvm::Value *Ptr =
Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
Value *Length =
>From 8619211c1201d26cdefbd502909ab541e3cc5e97 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 19:22:05 -0700
Subject: [PATCH 12/25] Early exit
---
clang/lib/CodeGen/CodeGenFunction.cpp | 49 +++++++++++++--------------
1 file changed, 24 insertions(+), 25 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 2c880eafb8f1e..af5ceb563681a 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2906,6 +2906,9 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
.parseTargetAttr(Options[Index].Conditions.Features[0])
.Features;
+ if (TargetAttrFeats.empty())
+ continue;
+
// Two conditions need to be checked for the current version:
//
// 1. LengthCondition: The maximum group ID of the required extension
@@ -2929,39 +2932,35 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
// ...
// else
// return DefaultVersion;
- if (!TargetAttrFeats.empty()) {
- llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
+ llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
- for (auto Feat : TargetAttrFeats)
- CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
+ for (auto Feat : TargetAttrFeats)
+ CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
- llvm::BasicBlock *FeatsCondBB =
- createBasicBlock("resovler_cond", Resolver);
+ llvm::BasicBlock *FeatsCondBB = createBasicBlock("resovler_cond", Resolver);
- Builder.SetInsertPoint(FeatsCondBB);
- unsigned MaxGroupIDUsed = 0;
- llvm::Value *FeatsCondition =
- EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
+ Builder.SetInsertPoint(FeatsCondBB);
+ unsigned MaxGroupIDUsed = 0;
+ llvm::Value *FeatsCondition =
+ EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
- Builder.SetInsertPoint(CurBlock);
- llvm::Value *MaxGroupLengthCondition =
- EmitRISCVFeatureBitsLength(MaxGroupIDUsed);
+ Builder.SetInsertPoint(CurBlock);
+ llvm::Value *MaxGroupLengthCondition =
+ EmitRISCVFeatureBitsLength(MaxGroupIDUsed);
- llvm::BasicBlock *RetBlock =
- createBasicBlock("resolver_return", Resolver);
- CGBuilderTy RetBuilder(*this, RetBlock);
- CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder,
- Options[Index].Function, SupportsIFunc);
- llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver);
+ llvm::BasicBlock *RetBlock = createBasicBlock("resolver_return", Resolver);
+ CGBuilderTy RetBuilder(*this, RetBlock);
+ CreateMultiVersionResolverReturn(CGM, Resolver, RetBuilder,
+ Options[Index].Function, SupportsIFunc);
+ llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver);
- Builder.SetInsertPoint(CurBlock);
- Builder.CreateCondBr(MaxGroupLengthCondition, FeatsCondBB, ElseBlock);
+ Builder.SetInsertPoint(CurBlock);
+ Builder.CreateCondBr(MaxGroupLengthCondition, FeatsCondBB, ElseBlock);
- Builder.SetInsertPoint(FeatsCondBB);
- Builder.CreateCondBr(FeatsCondition, RetBlock, ElseBlock);
+ Builder.SetInsertPoint(FeatsCondBB);
+ Builder.CreateCondBr(FeatsCondition, RetBlock, ElseBlock);
- CurBlock = ElseBlock;
- }
+ CurBlock = ElseBlock;
}
// Finally, emit the default one.
>From 993789fb6b832daedf6aa1232d11345a8cab05f1 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 19:22:48 -0700
Subject: [PATCH 13/25] Fix typo
---
clang/lib/CodeGen/CodeGenFunction.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index af5ceb563681a..3e9621c492d1d 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2937,7 +2937,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
for (auto Feat : TargetAttrFeats)
CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
- llvm::BasicBlock *FeatsCondBB = createBasicBlock("resovler_cond", Resolver);
+ llvm::BasicBlock *FeatsCondBB = createBasicBlock("resolver_cond", Resolver);
Builder.SetInsertPoint(FeatsCondBB);
unsigned MaxGroupIDUsed = 0;
>From 96533e70ba7232f0f21068f7f06d77f7c6aaecc8 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 21:41:34 -0700
Subject: [PATCH 14/25] Change ULT operand order and update testcase
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/test/CodeGen/attr-target-clones-riscv.c | 36 +++++++++----------
.../CodeGenCXX/attr-target-clones-riscv.cpp | 36 +++++++++----------
3 files changed, 37 insertions(+), 37 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ca69e76cbcfcd..ecfecb81a5263 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14431,7 +14431,7 @@ Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
Value *UsedMaxGroupID = Builder.getInt64(MaxGroupIDUsed);
Value *GroupIDResult =
- Builder.CreateICmpULT(UsedMaxGroupID, LoadMaxGroupID());
+ Builder.CreateICmpULT(LoadMaxGroupID(), UsedMaxGroupID);
return GroupIDResult;
}
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index 27e8d20f7ba17..81474ed7724a2 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -40,9 +40,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096
@@ -64,9 +64,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456
@@ -76,9 +76,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret ptr @"foo2.arch=+zbb"
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 0, [[TMP6]]
-// CHECK-NEXT: br i1 [[TMP7]], label [[RESOVLER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
-// CHECK: resovler_cond1:
+// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 [[TMP6]], 0
+// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
+// CHECK: resolver_cond1:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096
@@ -100,9 +100,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12
@@ -124,9 +124,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016
@@ -160,9 +160,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index 6bac679cf1425..63ba1836056a7 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -40,9 +40,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096
@@ -64,9 +64,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456
@@ -76,9 +76,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+zbb"
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 0, [[TMP6]]
-// CHECK-NEXT: br i1 [[TMP7]], label [[RESOVLER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
-// CHECK: resovler_cond1:
+// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 [[TMP6]], 0
+// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
+// CHECK: resolver_cond1:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096
// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096
@@ -100,9 +100,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12
@@ -124,9 +124,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016
@@ -160,9 +160,9 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 0, [[TMP0]]
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOVLER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resovler_cond:
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
+// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488
// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488
>From 50852119612f8f6ab5142e26b0f185a9fc218c5b Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 22:11:40 -0700
Subject: [PATCH 15/25] less than -> greater than
---
clang/lib/CodeGen/CGBuiltin.cpp | 2 +-
clang/test/CodeGen/attr-target-clones-riscv.c | 12 ++++++------
clang/test/CodeGenCXX/attr-target-clones-riscv.cpp | 12 ++++++------
3 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ecfecb81a5263..8127df267c0ad 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14431,7 +14431,7 @@ Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
Value *UsedMaxGroupID = Builder.getInt64(MaxGroupIDUsed);
Value *GroupIDResult =
- Builder.CreateICmpULT(LoadMaxGroupID(), UsedMaxGroupID);
+ Builder.CreateICmpUGT(LoadMaxGroupID(), UsedMaxGroupID);
return GroupIDResult;
}
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index 81474ed7724a2..d3e0c63baa8a2 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -40,7 +40,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -64,7 +64,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -76,7 +76,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret ptr @"foo2.arch=+zbb"
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 [[TMP6]], 0
+// CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP6]], 0
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
// CHECK: resolver_cond1:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -100,7 +100,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -124,7 +124,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -160,7 +160,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index 63ba1836056a7..2b8c1650fd1b1 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -40,7 +40,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -64,7 +64,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -76,7 +76,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+zbb"
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = icmp ult i64 [[TMP6]], 0
+// CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP6]], 0
// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
// CHECK: resolver_cond1:
// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -100,7 +100,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -124,7 +124,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
@@ -160,7 +160,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 0
+// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
>From 64dc5908e035098ffa0317df4dc027e9ccde93cc Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 22:35:25 -0700
Subject: [PATCH 16/25] Update attr-target-clones-riscv-invalid.c
---
clang/test/CodeGen/attr-target-clones-riscv-invalid.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/clang/test/CodeGen/attr-target-clones-riscv-invalid.c b/clang/test/CodeGen/attr-target-clones-riscv-invalid.c
index f5e8f40d7a8f3..a84a0608044b5 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv-invalid.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv-invalid.c
@@ -1,8 +1,8 @@
// RUN: not %clang_cc1 -triple riscv64 -target-feature +i -emit-llvm -o - %s 2>&1 | FileCheck %s --check-prefix=CHECK-UNSUPPORT-OS
// CHECK-UNSUPPORT-OS: error: target_clones is currently only supported on Linux
-__attribute__((target_clones("default", "arch=+c"))) int foo2(void) {
+__attribute__((target_clones("default", "arch=+c"))) int foo(void) {
return 2;
}
-int bar() { return foo1()+foo2(); }
+int bar() { return foo(); }
>From 68744ef84c7f79304b8c1855abe57605c09d01db Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 17 Jul 2024 23:06:40 -0700
Subject: [PATCH 17/25] Use unsigned instead of int
---
clang/lib/CodeGen/CodeGenFunction.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 3e9621c492d1d..f874664f8ab43 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2888,7 +2888,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
bool SupportsIFunc = getContext().getTargetInfo().supportsIFunc();
bool HasDefault = false;
- int DefaultIndex = 0;
+ unsigned DefaultIndex = 0;
// Check the each candidate function.
for (unsigned Index = 0; Index < Options.size(); Index++) {
>From 9079fe3f82e183e5be44580a79e38b4050d3fc0d Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sat, 20 Jul 2024 06:35:41 -0700
Subject: [PATCH 18/25] Filter +features
---
clang/lib/CodeGen/CodeGenFunction.cpp | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index f874664f8ab43..d299138efbba1 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2934,8 +2934,12 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
// return DefaultVersion;
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
- for (auto Feat : TargetAttrFeats)
- CurrTargetAttrFeats.push_back(StringRef(Feat).substr(1));
+ for (auto Feat : TargetAttrFeats) {
+ StringRef CurrFeat = Feat;
+ if (!CurrFeat.starts_with("+"))
+ continue;
+ CurrTargetAttrFeats.push_back(CurrFeat.substr(1));
+ }
llvm::BasicBlock *FeatsCondBB = createBasicBlock("resolver_cond", Resolver);
>From b55b21121f27de3ae5ff5a445f3b9057ca295ed7 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sat, 20 Jul 2024 07:00:08 -0700
Subject: [PATCH 19/25] Make mangling name normalized
---
clang/lib/CodeGen/Targets/RISCV.cpp | 14 ++++-
clang/test/CodeGen/attr-target-clones-riscv.c | 58 +++++++++++++++----
.../CodeGenCXX/attr-target-clones-riscv.cpp | 56 ++++++++++++++----
3 files changed, 106 insertions(+), 22 deletions(-)
diff --git a/clang/lib/CodeGen/Targets/RISCV.cpp b/clang/lib/CodeGen/Targets/RISCV.cpp
index ba81bf7d1dd0a..22171c1bbf563 100644
--- a/clang/lib/CodeGen/Targets/RISCV.cpp
+++ b/clang/lib/CodeGen/Targets/RISCV.cpp
@@ -86,7 +86,19 @@ void RISCVABIInfo::appendAttributeMangling(StringRef AttrStr,
}
Out << '.';
- Out << AttrStr;
+
+ SmallVector<StringRef, 8> Features;
+ AttrStr.consume_front("arch=");
+ AttrStr.split(Features, ",");
+
+ llvm::sort(Features, [](const StringRef LHS, const StringRef RHS) {
+ return LHS.compare(RHS) < 0;
+ });
+
+ for (auto Feat : Features) {
+ Feat.consume_front("+");
+ Out << "_" << Feat;
+ }
}
void RISCVABIInfo::computeInfo(CGFunctionInfo &FI) const {
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index d3e0c63baa8a2..4a9465348256b 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -36,6 +36,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 1
//
//
+// CHECK-LABEL: define dso_local signext i32 @foo1._m(
+// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 1
+//
+//
// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -49,7 +55,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"foo1.arch=+m"
+// CHECK-NEXT: ret ptr @foo1._m
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @foo1.default
//
@@ -60,6 +66,18 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 2
//
//
+// CHECK-LABEL: define dso_local signext i32 @foo2._zbb(
+// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
+// CHECK-LABEL: define dso_local signext i32 @foo2._m(
+// CHECK-SAME: ) #[[ATTR1]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -73,7 +91,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"foo2.arch=+zbb"
+// CHECK-NEXT: ret ptr @foo2._zbb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP6]], 0
@@ -85,7 +103,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]]
// CHECK: resolver_return2:
-// CHECK-NEXT: ret ptr @"foo2.arch=+m"
+// CHECK-NEXT: ret ptr @foo2._m
// CHECK: resolver_else3:
// CHECK-NEXT: ret ptr @foo2.default
//
@@ -96,6 +114,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 3
//
//
+// CHECK-LABEL: define dso_local signext i32 @foo3._c_zbb(
+// CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 3
+//
+//
// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -109,7 +133,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"foo3.arch=+zbb,+c"
+// CHECK-NEXT: ret ptr @foo3._c_zbb
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @foo3.default
//
@@ -120,6 +144,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 4
//
//
+// CHECK-LABEL: define dso_local signext i32 @foo4._v_zbb(
+// CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 4
+//
+//
// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -133,7 +163,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"foo4.arch=+zbb,+v"
+// CHECK-NEXT: ret ptr @foo4._v_zbb
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @foo4.default
//
@@ -156,6 +186,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 2
//
//
+// CHECK-LABEL: define dso_local signext i32 @foo6._zvkt(
+// CHECK-SAME: ) #[[ATTR5:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -169,7 +205,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"foo6.arch=+zvkt"
+// CHECK-NEXT: ret ptr @foo6._zvkt
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @foo6.default
//
@@ -190,11 +226,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
//.
// CHECK: attributes #[[ATTR0]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i" }
-// CHECK: attributes #[[ATTR1:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
-// CHECK: attributes #[[ATTR2:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" }
-// CHECK: attributes #[[ATTR3:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb" }
-// CHECK: attributes #[[ATTR4:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zbb,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
-// CHECK: attributes #[[ATTR5:[0-9]+]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zvkt" }
+// CHECK: attributes #[[ATTR1]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
+// CHECK: attributes #[[ATTR2]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zbb" }
+// CHECK: attributes #[[ATTR3]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+zbb" }
+// CHECK: attributes #[[ATTR4]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+v,+zbb,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #[[ATTR5]] = { noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+zvkt" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index 2b8c1650fd1b1..291175f695fbc 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -36,6 +36,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 1
//
//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo1v._m(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 1
+//
+//
// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -49,7 +55,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"_Z4foo1v.arch=+m"
+// CHECK-NEXT: ret ptr @_Z4foo1v._m
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @_Z4foo1v.default
//
@@ -60,6 +66,18 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 2
//
//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._zbb(
+// CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo2v._m(
+// CHECK-SAME: ) #[[ATTR0]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -73,7 +91,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+zbb"
+// CHECK-NEXT: ret ptr @_Z4foo2v._zbb
// CHECK: resolver_else:
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
// CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP6]], 0
@@ -85,7 +103,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]]
// CHECK: resolver_return2:
-// CHECK-NEXT: ret ptr @"_Z4foo2v.arch=+m"
+// CHECK-NEXT: ret ptr @_Z4foo2v._m
// CHECK: resolver_else3:
// CHECK-NEXT: ret ptr @_Z4foo2v.default
//
@@ -96,6 +114,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 3
//
//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo3v._c_zbb(
+// CHECK-SAME: ) #[[ATTR2:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 3
+//
+//
// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -109,7 +133,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"_Z4foo3v.arch=+zbb,+c"
+// CHECK-NEXT: ret ptr @_Z4foo3v._c_zbb
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @_Z4foo3v.default
//
@@ -120,6 +144,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 4
//
//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo4v._v_zbb(
+// CHECK-SAME: ) #[[ATTR3:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 4
+//
+//
// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -133,7 +163,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"_Z4foo4v.arch=+zbb,+v"
+// CHECK-NEXT: ret ptr @_Z4foo4v._v_zbb
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @_Z4foo4v.default
//
@@ -156,6 +186,12 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: ret i32 2
//
//
+// CHECK-LABEL: define dso_local noundef signext i32 @_Z4foo6v._zvkt(
+// CHECK-SAME: ) #[[ATTR4:[0-9]+]] {
+// CHECK-NEXT: entry:
+// CHECK-NEXT: ret i32 2
+//
+//
// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
@@ -169,7 +205,7 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
-// CHECK-NEXT: ret ptr @"_Z4foo6v.arch=+zvkt"
+// CHECK-NEXT: ret ptr @_Z4foo6v._zvkt
// CHECK: resolver_else:
// CHECK-NEXT: ret ptr @_Z4foo6v.default
//
@@ -190,10 +226,10 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
//
//.
// CHECK: attributes #[[ATTR0]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul" }
-// CHECK: attributes #[[ATTR1:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }
-// CHECK: attributes #[[ATTR2:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" }
-// CHECK: attributes #[[ATTR3:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
-// CHECK: attributes #[[ATTR4:[0-9]+]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" }
+// CHECK: attributes #[[ATTR1]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zbb,+zmmul" }
+// CHECK: attributes #[[ATTR2]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+c,+i,+m,+zbb,+zmmul" }
+// CHECK: attributes #[[ATTR3]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+d,+f,+i,+m,+v,+zbb,+zicsr,+zmmul,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b" }
+// CHECK: attributes #[[ATTR4]] = { mustprogress noinline nounwind optnone "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-features"="+64bit,+i,+m,+zmmul,+zvkt" }
//.
// CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4}
// CHECK: [[META1:![0-9]+]] = !{i32 1, !"target-abi", !"lp64"}
>From 4c39ce56e0b1fb437a241aa3e22a081a16d4f730 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 21 Jul 2024 06:16:33 -0700
Subject: [PATCH 20/25] Fix StringRef reference issue
---
clang/lib/CodeGen/CodeGenFunction.cpp | 2 +-
clang/test/CodeGen/attr-target-clones-riscv.c | 8 ++++----
clang/test/CodeGenCXX/attr-target-clones-riscv.cpp | 8 ++++----
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index d299138efbba1..59cecc5d3bd3b 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2934,7 +2934,7 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
// return DefaultVersion;
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
- for (auto Feat : TargetAttrFeats) {
+ for (auto &Feat : TargetAttrFeats) {
StringRef CurrFeat = Feat;
if (!CurrFeat.starts_with("+"))
continue;
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index 4a9465348256b..225d47473dfc0 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -128,8 +128,8 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435460
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435460
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
@@ -158,8 +158,8 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 270532608
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 270532608
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index 291175f695fbc..f7a4bd1404ac8 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -128,8 +128,8 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 12
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 12
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435460
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435460
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
@@ -158,8 +158,8 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_cond:
// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 69206016
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 69206016
+// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 270532608
+// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 270532608
// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
// CHECK: resolver_return:
>From 8a026c99b8cf3a2266c66921acb5b0047cab511c Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 21 Jul 2024 06:16:59 -0700
Subject: [PATCH 21/25] Make unsupport bitmask raise warning instead of
assertion
---
clang/include/clang/Sema/SemaRISCV.h | 1 +
clang/lib/CodeGen/CGBuiltin.cpp | 16 +++++++++----
clang/lib/Sema/SemaDeclAttr.cpp | 6 ++++-
clang/lib/Sema/SemaRISCV.cpp | 13 +++++++++++
.../test/SemaCXX/attr-target-clones-riscv.cpp | 3 +++
.../llvm/TargetParser/RISCVTargetParser.h | 5 +++-
llvm/lib/TargetParser/RISCVTargetParser.cpp | 23 +++++++++++--------
7 files changed, 52 insertions(+), 15 deletions(-)
diff --git a/clang/include/clang/Sema/SemaRISCV.h b/clang/include/clang/Sema/SemaRISCV.h
index 48d15c411bddd..9798328361f8e 100644
--- a/clang/include/clang/Sema/SemaRISCV.h
+++ b/clang/include/clang/Sema/SemaRISCV.h
@@ -40,6 +40,7 @@ class SemaRISCV : public SemaBase {
void handleInterruptAttr(Decl *D, const ParsedAttr &AL);
bool isAliasValid(unsigned BuiltinID, StringRef AliasName);
+ bool isValidFMVExtension(StringRef Ext);
/// Indicate RISC-V vector builtin functions enabled or not.
bool DeclareRVVBuiltins = false;
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index 8127df267c0ad..c4a6e728de797 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14394,14 +14394,22 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
return FeaturesBit;
};
- SmallVector<uint64_t> RequireFeatureBits =
+ Expected<SmallVector<uint64_t>> RequireFeatureBits =
llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs);
+
+ // Should guard by Sema part, but if we got the extension without bitmask.
+ // Return false for it.
+ if (!RequireFeatureBits) {
+ consumeError(RequireFeatureBits.takeError());
+ return Builder.getFalse();
+ }
+
Value *Result = Builder.getTrue();
- for (unsigned i = 0; i < RequireFeatureBits.size(); i++) {
- if (!RequireFeatureBits[i])
+ for (unsigned i = 0; i < RequireFeatureBits.get().size(); i++) {
+ if (!RequireFeatureBits.get()[i])
continue;
MaxGroupIDUsed = i;
- Value *Mask = Builder.getInt64(RequireFeatureBits[i]);
+ Value *Mask = Builder.getInt64(RequireFeatureBits.get()[i]);
Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask);
Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
Result = Builder.CreateAnd(Result, Cmp);
diff --git a/clang/lib/Sema/SemaDeclAttr.cpp b/clang/lib/Sema/SemaDeclAttr.cpp
index 33336272f1254..59eac42bfc591 100644
--- a/clang/lib/Sema/SemaDeclAttr.cpp
+++ b/clang/lib/Sema/SemaDeclAttr.cpp
@@ -3140,7 +3140,11 @@ bool Sema::checkTargetClonesAttrString(
ParsedTargetAttr TargetAttr =
Context.getTargetInfo().parseTargetAttr(Str);
- if (TargetAttr.Features.empty())
+
+ if (TargetAttr.Features.empty() ||
+ llvm::any_of(TargetAttr.Features, [&](const StringRef Ext) {
+ return !RISCV().isValidFMVExtension(Ext);
+ }))
return Diag(CurLoc, diag::warn_unsupported_target_attribute)
<< Unsupported << None << Str << TargetClones;
} else if (Str == "default") {
diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp
index f1c7c0516e671..326da079f3037 100644
--- a/clang/lib/Sema/SemaRISCV.cpp
+++ b/clang/lib/Sema/SemaRISCV.cpp
@@ -1486,6 +1486,19 @@ bool SemaRISCV::isAliasValid(unsigned BuiltinID, StringRef AliasName) {
BuiltinID <= RISCV::LastRVVBuiltin;
}
+bool SemaRISCV::isValidFMVExtension(StringRef Ext) {
+ if (Ext.empty())
+ return false;
+
+ Ext.consume_front("+");
+ auto ExtBitmask = llvm::RISCV::getExtensionBitmask(Ext);
+
+ if (Ext.equals_insensitive(ExtBitmask.Name))
+ return true;
+
+ return false;
+}
+
SemaRISCV::SemaRISCV(Sema &S) : SemaBase(S) {}
} // namespace clang
diff --git a/clang/test/SemaCXX/attr-target-clones-riscv.cpp b/clang/test/SemaCXX/attr-target-clones-riscv.cpp
index edee5f7c231e9..e6122b7eed493 100644
--- a/clang/test/SemaCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/SemaCXX/attr-target-clones-riscv.cpp
@@ -21,6 +21,9 @@ void __attribute__((target_clones("default", "+c"))) invaildVersion() {}
// expected-warning at +1 {{unsupported 'arch=rv64g' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
void __attribute__((target_clones("default", "arch=rv64g"))) fullArchString() {}
+// expected-warning at +1 {{unsupported 'arch=+zicsr' in the 'target_clones' attribute string; 'target_clones' attribute ignored}}
+void __attribute__((target_clones("default", "arch=+zicsr"))) UnsupportBitMaskExt() {}
+
void lambda() {
// expected-error at +1 {{attribute 'target_clones' multiversioned functions do not yet support lambdas}}
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 7346d25957ce8..1f84b5031dd01 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -47,7 +47,10 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool hasFastScalarUnalignedAccess(StringRef CPU);
bool hasFastVectorUnalignedAccess(StringRef CPU);
-llvm::SmallVector<uint64_t> getRequireFeatureBitMask(ArrayRef<StringRef>);
+Expected<llvm::SmallVector<uint64_t>>
+ getRequireFeatureBitMask(ArrayRef<StringRef>);
+RISCVExtensionBitmaskTable::RISCVExtensionBitmask
+getExtensionBitmask(StringRef ExtName);
} // namespace RISCV
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 56e4bd209d868..0a7e042fd97dc 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -14,6 +14,7 @@
#include "llvm/TargetParser/RISCVTargetParser.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringSwitch.h"
+#include "llvm/Support/Error.h"
#include "llvm/TargetParser/RISCVISAInfo.h"
#include "llvm/TargetParser/Triple.h"
@@ -144,26 +145,30 @@ struct LessExtName {
};
} // namespace
-static Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask>
+RISCVExtensionBitmaskTable::RISCVExtensionBitmask
getExtensionBitmask(StringRef ExtName) {
ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
RISCVExtensionBitmaskTable::ExtensionBitmask;
- auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
- if (I != ExtBitmasks.end())
- return *I;
+ for (auto ExtBitmask : ExtBitmasks) {
+ if (ExtName.equals_insensitive(ExtBitmask.Name)) {
+ return ExtBitmask;
+ }
+ }
- return createStringError("Unsupport extension");
+ return RISCVExtensionBitmaskTable::RISCVExtensionBitmask();
}
-llvm::SmallVector<uint64_t> getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
+Expected<llvm::SmallVector<uint64_t>>
+getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
llvm::SmallVector<uint64_t> BitMasks(RISCV::RISCVFeatureBitSize);
for (auto Ext : Exts) {
- Expected<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmask =
+ RISCVExtensionBitmaskTable::RISCVExtensionBitmask ExtBitmask =
getExtensionBitmask(Ext);
- assert(ExtBitmask && "This extension doesn't has bitmask.");
- BitMasks[ExtBitmask->GroupID] |= (1ULL << ExtBitmask->BitPosition);
+ if (!Ext.equals_insensitive(ExtBitmask.Name))
+ return createStringError("Unsupport bitmask");
+ BitMasks[ExtBitmask.GroupID] |= (1ULL << ExtBitmask.BitPosition);
}
return BitMasks;
>From 95575fc54343bdedbf5918889e8a538f8eccd31b Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 21 Jul 2024 06:45:05 -0700
Subject: [PATCH 22/25] Remove the length checking
---
clang/lib/CodeGen/CGBuiltin.cpp | 30 +------
clang/lib/CodeGen/CodeGenFunction.cpp | 31 +++----
clang/lib/CodeGen/CodeGenFunction.h | 4 +-
clang/test/CodeGen/attr-target-clones-riscv.c | 88 +++++++------------
.../CodeGenCXX/attr-target-clones-riscv.cpp | 88 +++++++------------
5 files changed, 76 insertions(+), 165 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index c4a6e728de797..c50316d4cde82 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14371,8 +14371,7 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef<StringRef> FeaturesStrs) {
return Result;
}
-Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
- unsigned &MaxGroupIDUsed) {
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs) {
const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
llvm::ArrayType *ArrayOfInt64Ty =
@@ -14408,7 +14407,6 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
for (unsigned i = 0; i < RequireFeatureBits.get().size(); i++) {
if (!RequireFeatureBits.get()[i])
continue;
- MaxGroupIDUsed = i;
Value *Mask = Builder.getInt64(RequireFeatureBits.get()[i]);
Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask);
Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
@@ -14418,32 +14416,6 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs,
return Result;
}
-Value *CodeGenFunction::EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed) {
-
- const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
- llvm::ArrayType *ArrayOfInt64Ty =
- llvm::ArrayType::get(Int64Ty, FeatureBitSize);
- llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
- llvm::Constant *RISCVFeaturesBits =
- CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
- cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true);
-
- auto LoadMaxGroupID = [&]() {
- llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(0)};
- llvm::Value *Ptr =
- Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
- Value *Length =
- Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
- return Length;
- };
-
- Value *UsedMaxGroupID = Builder.getInt64(MaxGroupIDUsed);
- Value *GroupIDResult =
- Builder.CreateICmpUGT(LoadMaxGroupID(), UsedMaxGroupID);
-
- return GroupIDResult;
-}
-
Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
const CallExpr *E) {
if (BuiltinID == Builtin::BI__builtin_cpu_is)
diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp
index 59cecc5d3bd3b..689fc7471a075 100644
--- a/clang/lib/CodeGen/CodeGenFunction.cpp
+++ b/clang/lib/CodeGen/CodeGenFunction.cpp
@@ -2909,29 +2909,29 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
if (TargetAttrFeats.empty())
continue;
- // Two conditions need to be checked for the current version:
- //
- // 1. LengthCondition: The maximum group ID of the required extension
- // does not exceed the runtime object's length.
- // __riscv_feature_bits.length > MAX_USED_GROUPID
+ // Only one conditions need to be checked for the current version:
//
// 2. FeaturesCondition: The bitmask of the required extension has been
// enabled by the runtime object.
// (__riscv_feature_bits.features[i] & REQUIRED_BITMASK) ==
// REQUIRED_BITMASK
//
- // When both conditions are met, return this version of the function.
+ // When condition is met, return this version of the function.
// Otherwise, try the next version.
//
- // if (LengthConditionVersion1 && FeaturesConditionVersion1)
+ // if (FeaturesConditionVersion1)
// return Version1;
- // else if (LengthConditionVersion2 && FeaturesConditionVersion2)
+ // else if (FeaturesConditionVersion2)
// return Version2;
- // else if (LengthConditionVersion3 && FeaturesConditionVersion3)
+ // else if (FeaturesConditionVersion3)
// return Version3;
// ...
// else
// return DefaultVersion;
+
+ // TODO: Add a condition to check the length due to runtime library version
+ // constraints. Without checking the length before access, it may result in
+ // accessing an incorrect memory address. Currently, the length must be 1.
llvm::SmallVector<StringRef, 8> CurrTargetAttrFeats;
for (auto &Feat : TargetAttrFeats) {
@@ -2941,16 +2941,8 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
CurrTargetAttrFeats.push_back(CurrFeat.substr(1));
}
- llvm::BasicBlock *FeatsCondBB = createBasicBlock("resolver_cond", Resolver);
-
- Builder.SetInsertPoint(FeatsCondBB);
- unsigned MaxGroupIDUsed = 0;
- llvm::Value *FeatsCondition =
- EmitRISCVCpuSupports(CurrTargetAttrFeats, MaxGroupIDUsed);
-
Builder.SetInsertPoint(CurBlock);
- llvm::Value *MaxGroupLengthCondition =
- EmitRISCVFeatureBitsLength(MaxGroupIDUsed);
+ llvm::Value *FeatsCondition = EmitRISCVCpuSupports(CurrTargetAttrFeats);
llvm::BasicBlock *RetBlock = createBasicBlock("resolver_return", Resolver);
CGBuilderTy RetBuilder(*this, RetBlock);
@@ -2959,9 +2951,6 @@ void CodeGenFunction::EmitRISCVMultiVersionResolver(
llvm::BasicBlock *ElseBlock = createBasicBlock("resolver_else", Resolver);
Builder.SetInsertPoint(CurBlock);
- Builder.CreateCondBr(MaxGroupLengthCondition, FeatsCondBB, ElseBlock);
-
- Builder.SetInsertPoint(FeatsCondBB);
Builder.CreateCondBr(FeatsCondition, RetBlock, ElseBlock);
CurBlock = ElseBlock;
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index 1f0d7c5d1c980..91255a0e3c552 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -5342,9 +5342,7 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitAArch64CpuSupports(const CallExpr *E);
llvm::Value *EmitAArch64CpuSupports(ArrayRef<StringRef> FeatureStrs);
llvm::Value *EmitRISCVCpuInit();
- llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeatureStrs,
- unsigned &MaxGroupIDUsed);
- llvm::Value *EmitRISCVFeatureBitsLength(unsigned MaxGroupIDUsed);
+ llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeatureStrs);
};
inline DominatingLLVMValue::saved_type
diff --git a/clang/test/CodeGen/attr-target-clones-riscv.c b/clang/test/CodeGen/attr-target-clones-riscv.c
index 225d47473dfc0..3628cc3906c55 100644
--- a/clang/test/CodeGen/attr-target-clones-riscv.c
+++ b/clang/test/CodeGen/attr-target-clones-riscv.c
@@ -45,15 +45,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @foo1.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo1._m
// CHECK: resolver_else:
@@ -81,30 +77,22 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @foo2.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo2._zbb
// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP6]], 0
-// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
-// CHECK: resolver_cond1:
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096
-// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096
-// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
-// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]]
-// CHECK: resolver_return2:
+// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
+// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
+// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
+// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @foo2._m
-// CHECK: resolver_else3:
+// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @foo2.default
//
//
@@ -123,15 +111,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @foo3.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435460
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435460
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo3._c_zbb
// CHECK: resolver_else:
@@ -153,15 +137,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @foo4.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 270532608
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 270532608
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 270532608
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo4._v_zbb
// CHECK: resolver_else:
@@ -195,15 +175,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @foo6.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @foo6._zvkt
// CHECK: resolver_else:
diff --git a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
index f7a4bd1404ac8..71a6d454062fd 100644
--- a/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
+++ b/clang/test/CodeGenCXX/attr-target-clones-riscv.cpp
@@ -45,15 +45,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @_Z4foo1v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 4096
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 4096
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 4096
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 4096
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_Z4foo1v._m
// CHECK: resolver_else:
@@ -81,30 +77,22 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @_Z4foo2v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435456
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435456
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435456
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435456
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_Z4foo2v._zbb
// CHECK: resolver_else:
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i64 [[TMP6]], 0
-// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_COND1:%.*]], label [[RESOLVER_ELSE3:%.*]]
-// CHECK: resolver_cond1:
-// CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4096
-// CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4096
-// CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]]
-// CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN2:%.*]], label [[RESOLVER_ELSE3]]
-// CHECK: resolver_return2:
+// CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 4096
+// CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 4096
+// CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]]
+// CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]]
+// CHECK: resolver_return1:
// CHECK-NEXT: ret ptr @_Z4foo2v._m
-// CHECK: resolver_else3:
+// CHECK: resolver_else2:
// CHECK-NEXT: ret ptr @_Z4foo2v.default
//
//
@@ -123,15 +111,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @_Z4foo3v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 268435460
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 268435460
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 268435460
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 268435460
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_Z4foo3v._c_zbb
// CHECK: resolver_else:
@@ -153,15 +137,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @_Z4foo4v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 270532608
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 270532608
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 270532608
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 270532608
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_Z4foo4v._v_zbb
// CHECK: resolver_else:
@@ -195,15 +175,11 @@ int bar() { return foo1() + foo2() + foo3() + foo4() + foo5(); }
// CHECK-LABEL: define weak_odr ptr @_Z4foo6v.resolver() comdat {
// CHECK-NEXT: resolver_entry:
// CHECK-NEXT: call void @__init_riscv_feature_bits()
-// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__riscv_feature_bits, align 8
-// CHECK-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 0
-// CHECK-NEXT: br i1 [[TMP1]], label [[RESOLVER_COND:%.*]], label [[RESOLVER_ELSE:%.*]]
-// CHECK: resolver_cond:
-// CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
-// CHECK-NEXT: [[TMP3:%.*]] = and i64 [[TMP2]], 576460752303423488
-// CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[TMP3]], 576460752303423488
-// CHECK-NEXT: [[TMP5:%.*]] = and i1 true, [[TMP4]]
-// CHECK-NEXT: br i1 [[TMP5]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE]]
+// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr getelementptr inbounds ({ i32, [1 x i64] }, ptr @__riscv_feature_bits, i32 0, i32 1, i32 0), align 8
+// CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 576460752303423488
+// CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 576460752303423488
+// CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]]
+// CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]]
// CHECK: resolver_return:
// CHECK-NEXT: ret ptr @_Z4foo6v._zvkt
// CHECK: resolver_else:
>From ff90fe883d34524efb55ff51b85edaac85f88329 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Sun, 21 Jul 2024 21:04:11 -0700
Subject: [PATCH 23/25] Rewrite getExtensionBitmask with lower_bound approach
---
llvm/lib/TargetParser/RISCVTargetParser.cpp | 8 +++-----
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index 0a7e042fd97dc..d3f3fd2e1c417 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -149,12 +149,10 @@ RISCVExtensionBitmaskTable::RISCVExtensionBitmask
getExtensionBitmask(StringRef ExtName) {
ArrayRef<RISCVExtensionBitmaskTable::RISCVExtensionBitmask> ExtBitmasks =
RISCVExtensionBitmaskTable::ExtensionBitmask;
+ auto *I = llvm::lower_bound(ExtBitmasks, ExtName, LessExtName());
- for (auto ExtBitmask : ExtBitmasks) {
- if (ExtName.equals_insensitive(ExtBitmask.Name)) {
- return ExtBitmask;
- }
- }
+ if (I != ExtBitmasks.end() && ExtName.equals_insensitive(I->Name))
+ return *I;
return RISCVExtensionBitmaskTable::RISCVExtensionBitmask();
}
>From d751bef4115fc5a8c92765847c4f4ff481a2bcb4 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Mon, 22 Jul 2024 03:41:07 -0700
Subject: [PATCH 24/25] Extract setupRISCVFeatureBits part
---
clang/lib/CodeGen/CGBuiltin.cpp | 29 +++++++++++++++++++++--------
clang/lib/CodeGen/CodeGenFunction.h | 1 +
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index c50316d4cde82..ba1b876eae192 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14371,23 +14371,36 @@ CodeGenFunction::EmitAArch64CpuSupports(ArrayRef<StringRef> FeaturesStrs) {
return Result;
}
-Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs) {
-
- const unsigned FeatureBitSize = llvm::RISCV::RISCVFeatureBitSize;
+static llvm::Type *getTypeOfRISCVFeatureBits(CodeGenModule &CGM,
+ llvm::LLVMContext &Context) {
+ llvm::Type *Int32Ty = llvm::Type::getInt32Ty(Context);
+ llvm::Type *Int64Ty = llvm::Type::getInt64Ty(Context);
llvm::ArrayType *ArrayOfInt64Ty =
- llvm::ArrayType::get(Int64Ty, FeatureBitSize);
+ llvm::ArrayType::get(Int64Ty, llvm::RISCV::RISCVFeatureBitSize);
llvm::Type *StructTy = llvm::StructType::get(Int32Ty, ArrayOfInt64Ty);
- llvm::Constant *RISCVFeaturesBits =
- CGM.CreateRuntimeVariable(StructTy, "__riscv_feature_bits");
+ return StructTy;
+}
+
+static llvm::Constant *setupRISCVFeatureBits(CodeGenModule &CGM,
+ llvm::LLVMContext &Context) {
+ llvm::Constant *RISCVFeaturesBits = CGM.CreateRuntimeVariable(
+ getTypeOfRISCVFeatureBits(CGM, Context), "__riscv_feature_bits");
cast<llvm::GlobalValue>(RISCVFeaturesBits)->setDSOLocal(true);
+ return RISCVFeaturesBits;
+}
+
+Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs) {
+ llvm::Constant *RISCVFeaturesBits =
+ setupRISCVFeatureBits(CGM, getLLVMContext());
auto LoadFeatureBit = [&](unsigned Index) {
// Create GEP then load.
Value *IndexVal = llvm::ConstantInt::get(Int32Ty, Index);
llvm::Value *GEPIndices[] = {Builder.getInt32(0), Builder.getInt32(1),
IndexVal};
- Value *Ptr =
- Builder.CreateInBoundsGEP(StructTy, RISCVFeaturesBits, GEPIndices);
+ Value *Ptr = Builder.CreateInBoundsGEP(
+ getTypeOfRISCVFeatureBits(CGM, getLLVMContext()), RISCVFeaturesBits,
+ GEPIndices);
Value *FeaturesBit =
Builder.CreateAlignedLoad(Int64Ty, Ptr, CharUnits::fromQuantity(8));
return FeaturesBit;
diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h
index 91255a0e3c552..b4bbd4eefc6dc 100644
--- a/clang/lib/CodeGen/CodeGenFunction.h
+++ b/clang/lib/CodeGen/CodeGenFunction.h
@@ -5343,6 +5343,7 @@ class CodeGenFunction : public CodeGenTypeCache {
llvm::Value *EmitAArch64CpuSupports(ArrayRef<StringRef> FeatureStrs);
llvm::Value *EmitRISCVCpuInit();
llvm::Value *EmitRISCVCpuSupports(ArrayRef<StringRef> FeatureStrs);
+ llvm::Value *EmitRISCVFeatureLength();
};
inline DominatingLLVMValue::saved_type
>From 370fd99188cfcedb3458f319d9cba7bc232c50e1 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Mon, 22 Jul 2024 04:22:15 -0700
Subject: [PATCH 25/25] Remove RequireFeatureBits and Use getExtensionBitmask
directly
---
clang/lib/CodeGen/CGBuiltin.cpp | 21 ++++++++++---------
.../llvm/TargetParser/RISCVTargetParser.h | 2 --
llvm/lib/TargetParser/RISCVTargetParser.cpp | 15 -------------
3 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp
index ba1b876eae192..1501b64396e01 100644
--- a/clang/lib/CodeGen/CGBuiltin.cpp
+++ b/clang/lib/CodeGen/CGBuiltin.cpp
@@ -14406,21 +14406,22 @@ Value *CodeGenFunction::EmitRISCVCpuSupports(ArrayRef<StringRef> FeaturesStrs) {
return FeaturesBit;
};
- Expected<SmallVector<uint64_t>> RequireFeatureBits =
- llvm::RISCV::getRequireFeatureBitMask(FeaturesStrs);
+ SmallVector<uint64_t> RequireBitMaskForEachGroup(
+ llvm::RISCV::RISCVFeatureBitSize);
- // Should guard by Sema part, but if we got the extension without bitmask.
- // Return false for it.
- if (!RequireFeatureBits) {
- consumeError(RequireFeatureBits.takeError());
- return Builder.getFalse();
+ for (auto Feat : FeaturesStrs) {
+ auto ExtBitMask = llvm::RISCV::getExtensionBitmask(Feat);
+ if (!Feat.equals_insensitive(ExtBitMask.Name))
+ return Builder.getFalse();
+ RequireBitMaskForEachGroup[ExtBitMask.GroupID] |=
+ (1ULL << ExtBitMask.BitPosition);
}
Value *Result = Builder.getTrue();
- for (unsigned i = 0; i < RequireFeatureBits.get().size(); i++) {
- if (!RequireFeatureBits.get()[i])
+ for (unsigned i = 0; i < RequireBitMaskForEachGroup.size(); i++) {
+ if (!RequireBitMaskForEachGroup[i])
continue;
- Value *Mask = Builder.getInt64(RequireFeatureBits.get()[i]);
+ Value *Mask = Builder.getInt64(RequireBitMaskForEachGroup[i]);
Value *Bitset = Builder.CreateAnd(LoadFeatureBit(i), Mask);
Value *Cmp = Builder.CreateICmpEQ(Bitset, Mask);
Result = Builder.CreateAnd(Result, Cmp);
diff --git a/llvm/include/llvm/TargetParser/RISCVTargetParser.h b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
index 1f84b5031dd01..649cb1a95dc25 100644
--- a/llvm/include/llvm/TargetParser/RISCVTargetParser.h
+++ b/llvm/include/llvm/TargetParser/RISCVTargetParser.h
@@ -47,8 +47,6 @@ void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64);
bool hasFastScalarUnalignedAccess(StringRef CPU);
bool hasFastVectorUnalignedAccess(StringRef CPU);
-Expected<llvm::SmallVector<uint64_t>>
- getRequireFeatureBitMask(ArrayRef<StringRef>);
RISCVExtensionBitmaskTable::RISCVExtensionBitmask
getExtensionBitmask(StringRef ExtName);
diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp
index d3f3fd2e1c417..5c5dc6bcc3782 100644
--- a/llvm/lib/TargetParser/RISCVTargetParser.cpp
+++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp
@@ -156,21 +156,6 @@ getExtensionBitmask(StringRef ExtName) {
return RISCVExtensionBitmaskTable::RISCVExtensionBitmask();
}
-
-Expected<llvm::SmallVector<uint64_t>>
-getRequireFeatureBitMask(ArrayRef<StringRef> Exts) {
- llvm::SmallVector<uint64_t> BitMasks(RISCV::RISCVFeatureBitSize);
-
- for (auto Ext : Exts) {
- RISCVExtensionBitmaskTable::RISCVExtensionBitmask ExtBitmask =
- getExtensionBitmask(Ext);
- if (!Ext.equals_insensitive(ExtBitmask.Name))
- return createStringError("Unsupport bitmask");
- BitMasks[ExtBitmask.GroupID] |= (1ULL << ExtBitmask.BitPosition);
- }
-
- return BitMasks;
-}
} // namespace RISCV
namespace RISCVVType {
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