[llvm] [SDag][ARM][RISCV] Lower 64-bit CTPOP into a libcall (PR #99752)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 21 05:46:26 PDT 2024
https://github.com/s-barannikov updated https://github.com/llvm/llvm-project/pull/99752
>From bb8a735facb710a07601d3bc9c45316f0de9d68d Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sat, 20 Jul 2024 13:11:56 +0300
Subject: [PATCH 1/4] [SelectionDAG] Allow lowering CTPOP into a libcall
Some in-tree targets (e.g. ARM) could benefit from this lowering,
at least in opt-size mode, but I don't know if the libcall
is available in their libgcc, so no tests.
---
llvm/include/llvm/IR/RuntimeLibcalls.def | 3 ++
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 38 +++++++++----------
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/llvm/include/llvm/IR/RuntimeLibcalls.def b/llvm/include/llvm/IR/RuntimeLibcalls.def
index 89aaf6d1ad83f..3dd75622b8e43 100644
--- a/llvm/include/llvm/IR/RuntimeLibcalls.def
+++ b/llvm/include/llvm/IR/RuntimeLibcalls.def
@@ -85,6 +85,9 @@ HANDLE_LIBCALL(NEG_I64, "__negdi2")
HANDLE_LIBCALL(CTLZ_I32, "__clzsi2")
HANDLE_LIBCALL(CTLZ_I64, "__clzdi2")
HANDLE_LIBCALL(CTLZ_I128, "__clzti2")
+HANDLE_LIBCALL(CTPOP_I32, "__popcountsi2")
+HANDLE_LIBCALL(CTPOP_I64, "__popcountdi2")
+HANDLE_LIBCALL(CTPOP_I128, "__popcountti2")
// Floating-point
HANDLE_LIBCALL(ADD_F32, "__addsf3")
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 9f515739ee048..bfae5671d8b77 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -140,12 +140,9 @@ class SelectionDAGLegalize {
RTLIB::Libcall Call_F128,
RTLIB::Libcall Call_PPCF128,
SmallVectorImpl<SDValue> &Results);
- SDValue ExpandIntLibCall(SDNode *Node, bool isSigned,
- RTLIB::Libcall Call_I8,
- RTLIB::Libcall Call_I16,
- RTLIB::Libcall Call_I32,
- RTLIB::Libcall Call_I64,
- RTLIB::Libcall Call_I128);
+ SDValue ExpandIntLibCall(SDNode *Node, bool IsSigned, RTLIB::Libcall Call_I8,
+ RTLIB::Libcall Call_I16, RTLIB::Libcall Call_I32,
+ RTLIB::Libcall Call_I64, RTLIB::Libcall Call_I128);
void ExpandArgFPLibCall(SDNode *Node,
RTLIB::Libcall Call_F32, RTLIB::Libcall Call_F64,
RTLIB::Libcall Call_F80, RTLIB::Libcall Call_F128,
@@ -2209,7 +2206,7 @@ void SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node,
ExpandFPLibCall(Node, LC, Results);
}
-SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
+SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode *Node, bool IsSigned,
RTLIB::Libcall Call_I8,
RTLIB::Libcall Call_I16,
RTLIB::Libcall Call_I32,
@@ -2224,7 +2221,9 @@ SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned,
case MVT::i64: LC = Call_I64; break;
case MVT::i128: LC = Call_I128; break;
}
- return ExpandLibCall(LC, Node, isSigned).first;
+ assert(LC != RTLIB::UNKNOWN_LIBCALL &&
+ "LibCall explicitly requested, but not available");
+ return ExpandLibCall(LC, Node, IsSigned).first;
}
/// Expand the node to a libcall based on first argument type (for instance
@@ -4980,19 +4979,16 @@ void SelectionDAGLegalize::ConvertNodeToLibcall(SDNode *Node) {
RTLIB::MUL_I64, RTLIB::MUL_I128));
break;
case ISD::CTLZ_ZERO_UNDEF:
- switch (Node->getSimpleValueType(0).SimpleTy) {
- default:
- llvm_unreachable("LibCall explicitly requested, but not available");
- case MVT::i32:
- Results.push_back(ExpandLibCall(RTLIB::CTLZ_I32, Node, false).first);
- break;
- case MVT::i64:
- Results.push_back(ExpandLibCall(RTLIB::CTLZ_I64, Node, false).first);
- break;
- case MVT::i128:
- Results.push_back(ExpandLibCall(RTLIB::CTLZ_I128, Node, false).first);
- break;
- }
+ Results.push_back(ExpandIntLibCall(Node, /*IsSigned=*/false,
+ RTLIB::UNKNOWN_LIBCALL,
+ RTLIB::UNKNOWN_LIBCALL, RTLIB::CTLZ_I32,
+ RTLIB::CTLZ_I64, RTLIB::CTLZ_I128));
+ break;
+ case ISD::CTPOP:
+ Results.push_back(ExpandIntLibCall(Node, /*IsSigned=*/false,
+ RTLIB::UNKNOWN_LIBCALL,
+ RTLIB::UNKNOWN_LIBCALL, RTLIB::CTPOP_I32,
+ RTLIB::CTPOP_I64, RTLIB::CTPOP_I128));
break;
case ISD::RESET_FPENV: {
// It is legalized to call 'fesetenv(FE_DFL_ENV)'. On most targets
>From 437a0e5d0e6f3688bc9d7de13a412bb234d7f574 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 21 Jul 2024 12:53:02 +0300
Subject: [PATCH 2/4] [ARM] Lower 32-bit CTPOP to a libcall
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 5 +-
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
llvm/test/CodeGen/ARM/popcnt.ll | 70 +++---------------
llvm/test/CodeGen/Thumb2/mve-ctpop.ll | 74 +++++++------------
4 files changed, 40 insertions(+), 111 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 140c97ccd90ba..a273fafd3f4d6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9127,8 +9127,9 @@ SDValue TargetLowering::expandCTTZ(SDNode *Node, SelectionDAG &DAG) const {
!isOperationLegalOrCustomOrPromote(ISD::XOR, VT)))
return SDValue();
- // Emit Table Lookup if ISD::CTLZ and ISD::CTPOP are not legal.
- if (!VT.isVector() && isOperationExpand(ISD::CTPOP, VT) &&
+ // Emit Table Lookup if ISD::CTPOP used in the fallback path below is going
+ // to be expanded or converted to a libcall.
+ if (!VT.isVector() && !isOperationLegalOrCustomOrPromote(ISD::CTPOP, VT) &&
!isOperationLegal(ISD::CTLZ, VT))
if (SDValue V = CTTZTableLookup(Node, DAG, dl, VT, Op, NumBitsPerElt))
return V;
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 2683b5741d459..2c0fd20e76d60 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -1204,7 +1204,7 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ROTR, VT, Expand);
}
setOperationAction(ISD::CTTZ, MVT::i32, Custom);
- setOperationAction(ISD::CTPOP, MVT::i32, Expand);
+ setOperationAction(ISD::CTPOP, MVT::i32, LibCall);
if (!Subtarget->hasV5TOps() || Subtarget->isThumb1Only()) {
setOperationAction(ISD::CTLZ, MVT::i32, Expand);
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, LibCall);
diff --git a/llvm/test/CodeGen/ARM/popcnt.ll b/llvm/test/CodeGen/ARM/popcnt.ll
index edcae5e141e73..d3d66d6d52979 100644
--- a/llvm/test/CodeGen/ARM/popcnt.ll
+++ b/llvm/test/CodeGen/ARM/popcnt.ll
@@ -324,30 +324,7 @@ define i32 @ctpop16(i16 %x) nounwind readnone {
define i32 @ctpop32(i32 %x) nounwind readnone {
; CHECK-LABEL: ctpop32:
; CHECK: @ %bb.0:
-; CHECK-NEXT: ldr r1, .LCPI22_0
-; CHECK-NEXT: ldr r2, .LCPI22_3
-; CHECK-NEXT: and r1, r1, r0, lsr #1
-; CHECK-NEXT: ldr r12, .LCPI22_1
-; CHECK-NEXT: sub r0, r0, r1
-; CHECK-NEXT: ldr r3, .LCPI22_2
-; CHECK-NEXT: and r1, r0, r2
-; CHECK-NEXT: and r0, r2, r0, lsr #2
-; CHECK-NEXT: add r0, r1, r0
-; CHECK-NEXT: add r0, r0, r0, lsr #4
-; CHECK-NEXT: and r0, r0, r12
-; CHECK-NEXT: mul r1, r0, r3
-; CHECK-NEXT: lsr r0, r1, #24
-; CHECK-NEXT: mov pc, lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI22_0:
-; CHECK-NEXT: .long 1431655765 @ 0x55555555
-; CHECK-NEXT: .LCPI22_1:
-; CHECK-NEXT: .long 252645135 @ 0xf0f0f0f
-; CHECK-NEXT: .LCPI22_2:
-; CHECK-NEXT: .long 16843009 @ 0x1010101
-; CHECK-NEXT: .LCPI22_3:
-; CHECK-NEXT: .long 858993459 @ 0x33333333
+; CHECK-NEXT: b __popcountsi2
%count = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %count
}
@@ -355,42 +332,17 @@ define i32 @ctpop32(i32 %x) nounwind readnone {
define i32 @ctpop64(i64 %x) nounwind readnone {
; CHECK-LABEL: ctpop64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, lr}
-; CHECK-NEXT: push {r4, lr}
-; CHECK-NEXT: ldr r2, .LCPI23_0
-; CHECK-NEXT: ldr r3, .LCPI23_3
-; CHECK-NEXT: and r4, r2, r0, lsr #1
-; CHECK-NEXT: and r2, r2, r1, lsr #1
-; CHECK-NEXT: sub r0, r0, r4
-; CHECK-NEXT: sub r1, r1, r2
-; CHECK-NEXT: and r4, r0, r3
-; CHECK-NEXT: and r2, r1, r3
-; CHECK-NEXT: and r0, r3, r0, lsr #2
-; CHECK-NEXT: and r1, r3, r1, lsr #2
-; CHECK-NEXT: add r0, r4, r0
-; CHECK-NEXT: ldr lr, .LCPI23_1
-; CHECK-NEXT: add r1, r2, r1
-; CHECK-NEXT: ldr r12, .LCPI23_2
-; CHECK-NEXT: add r0, r0, r0, lsr #4
-; CHECK-NEXT: and r0, r0, lr
-; CHECK-NEXT: add r1, r1, r1, lsr #4
-; CHECK-NEXT: mul r2, r0, r12
-; CHECK-NEXT: and r0, r1, lr
-; CHECK-NEXT: mul r1, r0, r12
-; CHECK-NEXT: lsr r0, r2, #24
-; CHECK-NEXT: add r0, r0, r1, lsr #24
-; CHECK-NEXT: pop {r4, lr}
+; CHECK-NEXT: .save {r4, r5, r11, lr}
+; CHECK-NEXT: push {r4, r5, r11, lr}
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bl __popcountsi2
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: bl __popcountsi2
+; CHECK-NEXT: add r0, r0, r5
+; CHECK-NEXT: pop {r4, r5, r11, lr}
; CHECK-NEXT: mov pc, lr
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI23_0:
-; CHECK-NEXT: .long 1431655765 @ 0x55555555
-; CHECK-NEXT: .LCPI23_1:
-; CHECK-NEXT: .long 252645135 @ 0xf0f0f0f
-; CHECK-NEXT: .LCPI23_2:
-; CHECK-NEXT: .long 16843009 @ 0x1010101
-; CHECK-NEXT: .LCPI23_3:
-; CHECK-NEXT: .long 858993459 @ 0x33333333
%count = tail call i64 @llvm.ctpop.i64(i64 %x)
%conv = trunc i64 %count to i32
ret i32 %conv
diff --git a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
index 724bd4f7963b8..dcba42db886ae 100644
--- a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
@@ -1,58 +1,34 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; NOTE: Assertions have been autoenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
; CHECK-LABEL: ctpop_2i64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r7, lr}
-; CHECK-NEXT: push {r4, r5, r7, lr}
-; CHECK-NEXT: vmov r1, r2, d1
-; CHECK-NEXT: mov.w lr, #1431655765
-; CHECK-NEXT: vmov r3, r4, d0
-; CHECK-NEXT: mov.w r12, #858993459
-; CHECK-NEXT: vldr s1, .LCPI0_0
-; CHECK-NEXT: vmov.f32 s3, s1
-; CHECK-NEXT: and.w r0, lr, r2, lsr #1
-; CHECK-NEXT: subs r0, r2, r0
-; CHECK-NEXT: and.w r2, r12, r0, lsr #2
-; CHECK-NEXT: bic r0, r0, #-858993460
-; CHECK-NEXT: add r0, r2
-; CHECK-NEXT: and.w r2, lr, r1, lsr #1
-; CHECK-NEXT: subs r1, r1, r2
-; CHECK-NEXT: add.w r0, r0, r0, lsr #4
-; CHECK-NEXT: and.w r2, r12, r1, lsr #2
-; CHECK-NEXT: bic r1, r1, #-858993460
-; CHECK-NEXT: add r1, r2
-; CHECK-NEXT: and.w r2, lr, r3, lsr #1
-; CHECK-NEXT: subs r2, r3, r2
-; CHECK-NEXT: bic r5, r0, #-252645136
-; CHECK-NEXT: add.w r1, r1, r1, lsr #4
-; CHECK-NEXT: mov.w r0, #16843009
-; CHECK-NEXT: and.w r3, r12, r2, lsr #2
-; CHECK-NEXT: bic r2, r2, #-858993460
-; CHECK-NEXT: add r2, r3
-; CHECK-NEXT: and.w r3, lr, r4, lsr #1
-; CHECK-NEXT: subs r3, r4, r3
-; CHECK-NEXT: bic r1, r1, #-252645136
-; CHECK-NEXT: add.w r2, r2, r2, lsr #4
-; CHECK-NEXT: muls r5, r0, r5
-; CHECK-NEXT: and.w r4, r12, r3, lsr #2
-; CHECK-NEXT: bic r3, r3, #-858993460
-; CHECK-NEXT: bic r2, r2, #-252645136
-; CHECK-NEXT: add r3, r4
-; CHECK-NEXT: muls r1, r0, r1
-; CHECK-NEXT: add.w r3, r3, r3, lsr #4
-; CHECK-NEXT: muls r2, r0, r2
-; CHECK-NEXT: bic r3, r3, #-252645136
-; CHECK-NEXT: muls r0, r3, r0
-; CHECK-NEXT: lsrs r1, r1, #24
-; CHECK-NEXT: add.w r1, r1, r5, lsr #24
-; CHECK-NEXT: lsrs r2, r2, #24
-; CHECK-NEXT: vmov s2, r1
-; CHECK-NEXT: add.w r0, r2, r0, lsr #24
-; CHECK-NEXT: vmov s0, r0
-; CHECK-NEXT: pop {r4, r5, r7, pc}
+; CHECK-NEXT: .save {r4, r5, r6, lr}
+; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: .vsave {d8, d9}
+; CHECK-NEXT: vpush {d8, d9}
+; CHECK-NEXT: vmov q4, q0
+; CHECK-NEXT: vmov r4, r0, d9
+; CHECK-NEXT: bl __popcountsi2
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: bl __popcountsi2
+; CHECK-NEXT: vmov r4, r1, d8
+; CHECK-NEXT: adds r6, r0, r5
+; CHECK-NEXT: vldr s17, .LCPI0_0
+; CHECK-NEXT: mov r0, r1
+; CHECK-NEXT: bl __popcountsi2
+; CHECK-NEXT: mov r5, r0
+; CHECK-NEXT: mov r0, r4
+; CHECK-NEXT: vmov s18, r6
+; CHECK-NEXT: bl __popcountsi2
+; CHECK-NEXT: add r0, r5
+; CHECK-NEXT: vmov.f32 s19, s17
+; CHECK-NEXT: vmov s16, r0
+; CHECK-NEXT: vmov q0, q4
+; CHECK-NEXT: vpop {d8, d9}
+; CHECK-NEXT: pop {r4, r5, r6, pc}
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI0_0:
>From f90a6b46a8a9639bad8f2aa826150a47727d6b82 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 21 Jul 2024 14:48:26 +0300
Subject: [PATCH 3/4] [SelectionDAG] Legalize wide CTPOP via a libcall
---
.../SelectionDAG/LegalizeIntegerTypes.cpp | 35 +++-
llvm/test/CodeGen/ARM/popcnt.ll | 14 +-
.../test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll | 39 +----
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll | 130 ++-------------
llvm/test/CodeGen/RISCV/rv32zbb.ll | 149 ++++--------------
llvm/test/CodeGen/Thumb2/mve-ctpop.ll | 36 ++---
6 files changed, 96 insertions(+), 307 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index af77b0070df0a..52286c00c635d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -3847,15 +3847,36 @@ void DAGTypeLegalizer::ExpandIntRes_CTLZ(SDNode *N,
Hi = DAG.getConstant(0, dl, NVT);
}
-void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N,
- SDValue &Lo, SDValue &Hi) {
- SDLoc dl(N);
+void DAGTypeLegalizer::ExpandIntRes_CTPOP(SDNode *N, SDValue &Lo, SDValue &Hi) {
+ SDValue Op = N->getOperand(0);
+ EVT VT = N->getValueType(0);
+ SDLoc DL(N);
+
+ // If the narrow CTPOP is not supported by the target, try to convert it
+ // to a libcall.
+ EVT ExpandedVT = TLI.getTypeToExpandTo(*DAG.getContext(), VT);
+ if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, ExpandedVT)) {
+ RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
+ if (VT == MVT::i32)
+ LC = RTLIB::CTPOP_I32;
+ else if (VT == MVT::i64)
+ LC = RTLIB::CTPOP_I64;
+ else if (VT == MVT::i128)
+ LC = RTLIB::CTPOP_I128;
+ if (LC != RTLIB::UNKNOWN_LIBCALL && TLI.getLibcallName(LC)) {
+ TargetLowering::MakeLibCallOptions CallOptions;
+ SDValue Res = TLI.makeLibCall(DAG, LC, VT, Op, CallOptions, DL).first;
+ SplitInteger(Res, Lo, Hi);
+ return;
+ }
+ }
+
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
- GetExpandedInteger(N->getOperand(0), Lo, Hi);
+ GetExpandedInteger(Op, Lo, Hi);
EVT NVT = Lo.getValueType();
- Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
- DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
- Hi = DAG.getConstant(0, dl, NVT);
+ Lo = DAG.getNode(ISD::ADD, DL, NVT, DAG.getNode(ISD::CTPOP, DL, NVT, Lo),
+ DAG.getNode(ISD::CTPOP, DL, NVT, Hi));
+ Hi = DAG.getConstant(0, DL, NVT);
}
void DAGTypeLegalizer::ExpandIntRes_CTTZ(SDNode *N,
diff --git a/llvm/test/CodeGen/ARM/popcnt.ll b/llvm/test/CodeGen/ARM/popcnt.ll
index d3d66d6d52979..6c01c516be9d2 100644
--- a/llvm/test/CodeGen/ARM/popcnt.ll
+++ b/llvm/test/CodeGen/ARM/popcnt.ll
@@ -332,16 +332,10 @@ define i32 @ctpop32(i32 %x) nounwind readnone {
define i32 @ctpop64(i64 %x) nounwind readnone {
; CHECK-LABEL: ctpop64:
; CHECK: @ %bb.0:
-; CHECK-NEXT: .save {r4, r5, r11, lr}
-; CHECK-NEXT: push {r4, r5, r11, lr}
-; CHECK-NEXT: mov r4, r0
-; CHECK-NEXT: mov r0, r1
-; CHECK-NEXT: bl __popcountsi2
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: bl __popcountsi2
-; CHECK-NEXT: add r0, r0, r5
-; CHECK-NEXT: pop {r4, r5, r11, lr}
+; CHECK-NEXT: .save {r11, lr}
+; CHECK-NEXT: push {r11, lr}
+; CHECK-NEXT: bl __popcountdi2
+; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: mov pc, lr
%count = tail call i64 @llvm.ctpop.i64(i64 %x)
%conv = trunc i64 %count to i32
diff --git a/llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
index f17cec231f323..5a33c9eb943f9 100644
--- a/llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/LoongArch/ctlz-cttz-ctpop.ll
@@ -297,40 +297,11 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
define i64 @test_ctpop_i64(i64 %a) nounwind {
; LA32-LABEL: test_ctpop_i64:
; LA32: # %bb.0:
-; LA32-NEXT: srli.w $a2, $a1, 1
-; LA32-NEXT: lu12i.w $a3, 349525
-; LA32-NEXT: ori $a3, $a3, 1365
-; LA32-NEXT: and $a2, $a2, $a3
-; LA32-NEXT: sub.w $a1, $a1, $a2
-; LA32-NEXT: lu12i.w $a2, 209715
-; LA32-NEXT: ori $a2, $a2, 819
-; LA32-NEXT: and $a4, $a1, $a2
-; LA32-NEXT: srli.w $a1, $a1, 2
-; LA32-NEXT: and $a1, $a1, $a2
-; LA32-NEXT: add.w $a1, $a4, $a1
-; LA32-NEXT: srli.w $a4, $a1, 4
-; LA32-NEXT: add.w $a1, $a1, $a4
-; LA32-NEXT: lu12i.w $a4, 61680
-; LA32-NEXT: ori $a4, $a4, 3855
-; LA32-NEXT: and $a1, $a1, $a4
-; LA32-NEXT: lu12i.w $a5, 4112
-; LA32-NEXT: ori $a5, $a5, 257
-; LA32-NEXT: mul.w $a1, $a1, $a5
-; LA32-NEXT: srli.w $a1, $a1, 24
-; LA32-NEXT: srli.w $a6, $a0, 1
-; LA32-NEXT: and $a3, $a6, $a3
-; LA32-NEXT: sub.w $a0, $a0, $a3
-; LA32-NEXT: and $a3, $a0, $a2
-; LA32-NEXT: srli.w $a0, $a0, 2
-; LA32-NEXT: and $a0, $a0, $a2
-; LA32-NEXT: add.w $a0, $a3, $a0
-; LA32-NEXT: srli.w $a2, $a0, 4
-; LA32-NEXT: add.w $a0, $a0, $a2
-; LA32-NEXT: and $a0, $a0, $a4
-; LA32-NEXT: mul.w $a0, $a0, $a5
-; LA32-NEXT: srli.w $a0, $a0, 24
-; LA32-NEXT: add.w $a0, $a0, $a1
-; LA32-NEXT: move $a1, $zero
+; LA32-NEXT: addi.w $sp, $sp, -16
+; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT: bl %plt(__popcountdi2)
+; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 16
; LA32-NEXT: ret
;
; LA64-LABEL: test_ctpop_i64:
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 8caa64c9572ce..24100654467f4 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -2560,47 +2560,14 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
}
define i64 @test_ctpop_i64(i64 %a) nounwind {
-; RV32I-LABEL: test_ctpop_i64:
-; RV32I: # %bb.0:
-; RV32I-NEXT: srli a2, a1, 1
-; RV32I-NEXT: lui a3, 349525
-; RV32I-NEXT: addi a3, a3, 1365
-; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: sub a1, a1, a2
-; RV32I-NEXT: lui a2, 209715
-; RV32I-NEXT: addi a2, a2, 819
-; RV32I-NEXT: and a4, a1, a2
-; RV32I-NEXT: srli a1, a1, 2
-; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: add a1, a4, a1
-; RV32I-NEXT: srli a4, a1, 4
-; RV32I-NEXT: add a1, a1, a4
-; RV32I-NEXT: lui a4, 61681
-; RV32I-NEXT: addi a4, a4, -241
-; RV32I-NEXT: and a1, a1, a4
-; RV32I-NEXT: slli a5, a1, 8
-; RV32I-NEXT: add a1, a1, a5
-; RV32I-NEXT: slli a5, a1, 16
-; RV32I-NEXT: add a1, a1, a5
-; RV32I-NEXT: srli a1, a1, 24
-; RV32I-NEXT: srli a5, a0, 1
-; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: sub a0, a0, a3
-; RV32I-NEXT: and a3, a0, a2
-; RV32I-NEXT: srli a0, a0, 2
-; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: add a0, a3, a0
-; RV32I-NEXT: srli a2, a0, 4
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: and a0, a0, a4
-; RV32I-NEXT: slli a2, a0, 8
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: slli a2, a0, 16
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: li a1, 0
-; RV32I-NEXT: ret
+; RV32_NOZBB-LABEL: test_ctpop_i64:
+; RV32_NOZBB: # %bb.0:
+; RV32_NOZBB-NEXT: addi sp, sp, -16
+; RV32_NOZBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32_NOZBB-NEXT: call __popcountdi2
+; RV32_NOZBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32_NOZBB-NEXT: addi sp, sp, 16
+; RV32_NOZBB-NEXT: ret
;
; RV64I-LABEL: test_ctpop_i64:
; RV64I: # %bb.0:
@@ -2635,44 +2602,6 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ret
;
-; RV32M-LABEL: test_ctpop_i64:
-; RV32M: # %bb.0:
-; RV32M-NEXT: srli a2, a1, 1
-; RV32M-NEXT: lui a3, 349525
-; RV32M-NEXT: addi a3, a3, 1365
-; RV32M-NEXT: and a2, a2, a3
-; RV32M-NEXT: sub a1, a1, a2
-; RV32M-NEXT: lui a2, 209715
-; RV32M-NEXT: addi a2, a2, 819
-; RV32M-NEXT: and a4, a1, a2
-; RV32M-NEXT: srli a1, a1, 2
-; RV32M-NEXT: and a1, a1, a2
-; RV32M-NEXT: add a1, a4, a1
-; RV32M-NEXT: srli a4, a1, 4
-; RV32M-NEXT: add a1, a1, a4
-; RV32M-NEXT: lui a4, 61681
-; RV32M-NEXT: addi a4, a4, -241
-; RV32M-NEXT: and a1, a1, a4
-; RV32M-NEXT: lui a5, 4112
-; RV32M-NEXT: addi a5, a5, 257
-; RV32M-NEXT: mul a1, a1, a5
-; RV32M-NEXT: srli a1, a1, 24
-; RV32M-NEXT: srli a6, a0, 1
-; RV32M-NEXT: and a3, a6, a3
-; RV32M-NEXT: sub a0, a0, a3
-; RV32M-NEXT: and a3, a0, a2
-; RV32M-NEXT: srli a0, a0, 2
-; RV32M-NEXT: and a0, a0, a2
-; RV32M-NEXT: add a0, a3, a0
-; RV32M-NEXT: srli a2, a0, 4
-; RV32M-NEXT: add a0, a0, a2
-; RV32M-NEXT: and a0, a0, a4
-; RV32M-NEXT: mul a0, a0, a5
-; RV32M-NEXT: srli a0, a0, 24
-; RV32M-NEXT: add a0, a0, a1
-; RV32M-NEXT: li a1, 0
-; RV32M-NEXT: ret
-;
; RV64M-LABEL: test_ctpop_i64:
; RV64M: # %bb.0:
; RV64M-NEXT: srli a1, a0, 1
@@ -2720,44 +2649,11 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
;
; RV32XTHEADBB-LABEL: test_ctpop_i64:
; RV32XTHEADBB: # %bb.0:
-; RV32XTHEADBB-NEXT: srli a2, a1, 1
-; RV32XTHEADBB-NEXT: lui a3, 349525
-; RV32XTHEADBB-NEXT: addi a3, a3, 1365
-; RV32XTHEADBB-NEXT: and a2, a2, a3
-; RV32XTHEADBB-NEXT: sub a1, a1, a2
-; RV32XTHEADBB-NEXT: lui a2, 209715
-; RV32XTHEADBB-NEXT: addi a2, a2, 819
-; RV32XTHEADBB-NEXT: and a4, a1, a2
-; RV32XTHEADBB-NEXT: srli a1, a1, 2
-; RV32XTHEADBB-NEXT: and a1, a1, a2
-; RV32XTHEADBB-NEXT: add a1, a4, a1
-; RV32XTHEADBB-NEXT: srli a4, a1, 4
-; RV32XTHEADBB-NEXT: add a1, a1, a4
-; RV32XTHEADBB-NEXT: lui a4, 61681
-; RV32XTHEADBB-NEXT: addi a4, a4, -241
-; RV32XTHEADBB-NEXT: and a1, a1, a4
-; RV32XTHEADBB-NEXT: slli a5, a1, 8
-; RV32XTHEADBB-NEXT: add a1, a1, a5
-; RV32XTHEADBB-NEXT: slli a5, a1, 16
-; RV32XTHEADBB-NEXT: add a1, a1, a5
-; RV32XTHEADBB-NEXT: srli a1, a1, 24
-; RV32XTHEADBB-NEXT: srli a5, a0, 1
-; RV32XTHEADBB-NEXT: and a3, a5, a3
-; RV32XTHEADBB-NEXT: sub a0, a0, a3
-; RV32XTHEADBB-NEXT: and a3, a0, a2
-; RV32XTHEADBB-NEXT: srli a0, a0, 2
-; RV32XTHEADBB-NEXT: and a0, a0, a2
-; RV32XTHEADBB-NEXT: add a0, a3, a0
-; RV32XTHEADBB-NEXT: srli a2, a0, 4
-; RV32XTHEADBB-NEXT: add a0, a0, a2
-; RV32XTHEADBB-NEXT: and a0, a0, a4
-; RV32XTHEADBB-NEXT: slli a2, a0, 8
-; RV32XTHEADBB-NEXT: add a0, a0, a2
-; RV32XTHEADBB-NEXT: slli a2, a0, 16
-; RV32XTHEADBB-NEXT: add a0, a0, a2
-; RV32XTHEADBB-NEXT: srli a0, a0, 24
-; RV32XTHEADBB-NEXT: add a0, a0, a1
-; RV32XTHEADBB-NEXT: li a1, 0
+; RV32XTHEADBB-NEXT: addi sp, sp, -16
+; RV32XTHEADBB-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32XTHEADBB-NEXT: call __popcountdi2
+; RV32XTHEADBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32XTHEADBB-NEXT: addi sp, sp, 16
; RV32XTHEADBB-NEXT: ret
;
; RV64XTHEADBB-LABEL: test_ctpop_i64:
diff --git a/llvm/test/CodeGen/RISCV/rv32zbb.ll b/llvm/test/CodeGen/RISCV/rv32zbb.ll
index cb9fc6c16333e..4a90bf5f055de 100644
--- a/llvm/test/CodeGen/RISCV/rv32zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv32zbb.ll
@@ -517,44 +517,11 @@ declare i64 @llvm.ctpop.i64(i64)
define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-LABEL: ctpop_i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: srli a2, a1, 1
-; RV32I-NEXT: lui a3, 349525
-; RV32I-NEXT: addi a3, a3, 1365
-; RV32I-NEXT: and a2, a2, a3
-; RV32I-NEXT: sub a1, a1, a2
-; RV32I-NEXT: lui a2, 209715
-; RV32I-NEXT: addi a2, a2, 819
-; RV32I-NEXT: and a4, a1, a2
-; RV32I-NEXT: srli a1, a1, 2
-; RV32I-NEXT: and a1, a1, a2
-; RV32I-NEXT: add a1, a4, a1
-; RV32I-NEXT: srli a4, a1, 4
-; RV32I-NEXT: add a1, a1, a4
-; RV32I-NEXT: lui a4, 61681
-; RV32I-NEXT: addi a4, a4, -241
-; RV32I-NEXT: and a1, a1, a4
-; RV32I-NEXT: slli a5, a1, 8
-; RV32I-NEXT: add a1, a1, a5
-; RV32I-NEXT: slli a5, a1, 16
-; RV32I-NEXT: add a1, a1, a5
-; RV32I-NEXT: srli a1, a1, 24
-; RV32I-NEXT: srli a5, a0, 1
-; RV32I-NEXT: and a3, a5, a3
-; RV32I-NEXT: sub a0, a0, a3
-; RV32I-NEXT: and a3, a0, a2
-; RV32I-NEXT: srli a0, a0, 2
-; RV32I-NEXT: and a0, a0, a2
-; RV32I-NEXT: add a0, a3, a0
-; RV32I-NEXT: srli a2, a0, 4
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: and a0, a0, a4
-; RV32I-NEXT: slli a2, a0, 8
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: slli a2, a0, 16
-; RV32I-NEXT: add a0, a0, a2
-; RV32I-NEXT: srli a0, a0, 24
-; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: li a1, 0
+; RV32I-NEXT: addi sp, sp, -16
+; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: call __popcountdi2
+; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: ctpop_i64:
@@ -682,82 +649,36 @@ declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {
; RV32I-LABEL: ctpop_v2i64:
; RV32I: # %bb.0:
-; RV32I-NEXT: lw a3, 4(a1)
-; RV32I-NEXT: lw a2, 8(a1)
-; RV32I-NEXT: lw a4, 12(a1)
-; RV32I-NEXT: lw a1, 0(a1)
-; RV32I-NEXT: srli a5, a3, 1
-; RV32I-NEXT: lui a6, 349525
-; RV32I-NEXT: addi a6, a6, 1365
-; RV32I-NEXT: and a5, a5, a6
-; RV32I-NEXT: sub a3, a3, a5
-; RV32I-NEXT: lui a5, 209715
-; RV32I-NEXT: addi a5, a5, 819
-; RV32I-NEXT: and a7, a3, a5
-; RV32I-NEXT: srli a3, a3, 2
-; RV32I-NEXT: and a3, a3, a5
-; RV32I-NEXT: add a3, a7, a3
-; RV32I-NEXT: srli a7, a3, 4
-; RV32I-NEXT: add a3, a3, a7
-; RV32I-NEXT: lui a7, 61681
-; RV32I-NEXT: addi a7, a7, -241
-; RV32I-NEXT: and a3, a3, a7
-; RV32I-NEXT: slli t0, a3, 8
-; RV32I-NEXT: add a3, a3, t0
-; RV32I-NEXT: slli t0, a3, 16
-; RV32I-NEXT: add a3, a3, t0
-; RV32I-NEXT: srli a3, a3, 24
-; RV32I-NEXT: srli t0, a1, 1
-; RV32I-NEXT: and t0, t0, a6
-; RV32I-NEXT: sub a1, a1, t0
-; RV32I-NEXT: and t0, a1, a5
-; RV32I-NEXT: srli a1, a1, 2
-; RV32I-NEXT: and a1, a1, a5
-; RV32I-NEXT: add a1, t0, a1
-; RV32I-NEXT: srli t0, a1, 4
-; RV32I-NEXT: add a1, a1, t0
-; RV32I-NEXT: and a1, a1, a7
-; RV32I-NEXT: slli t0, a1, 8
-; RV32I-NEXT: add a1, a1, t0
-; RV32I-NEXT: slli t0, a1, 16
-; RV32I-NEXT: add a1, a1, t0
-; RV32I-NEXT: srli a1, a1, 24
-; RV32I-NEXT: add a1, a1, a3
-; RV32I-NEXT: srli a3, a4, 1
-; RV32I-NEXT: and a3, a3, a6
-; RV32I-NEXT: sub a4, a4, a3
-; RV32I-NEXT: and a3, a4, a5
-; RV32I-NEXT: srli a4, a4, 2
-; RV32I-NEXT: and a4, a4, a5
-; RV32I-NEXT: add a3, a3, a4
-; RV32I-NEXT: srli a4, a3, 4
-; RV32I-NEXT: add a3, a3, a4
-; RV32I-NEXT: and a3, a3, a7
-; RV32I-NEXT: slli a4, a3, 8
-; RV32I-NEXT: add a3, a3, a4
-; RV32I-NEXT: slli a4, a3, 16
-; RV32I-NEXT: add a3, a3, a4
-; RV32I-NEXT: srli a3, a3, 24
-; RV32I-NEXT: srli a4, a2, 1
-; RV32I-NEXT: and a4, a4, a6
-; RV32I-NEXT: sub a2, a2, a4
-; RV32I-NEXT: and a4, a2, a5
-; RV32I-NEXT: srli a2, a2, 2
-; RV32I-NEXT: and a2, a2, a5
-; RV32I-NEXT: add a2, a4, a2
-; RV32I-NEXT: srli a4, a2, 4
-; RV32I-NEXT: add a2, a2, a4
-; RV32I-NEXT: and a2, a2, a7
-; RV32I-NEXT: slli a4, a2, 8
-; RV32I-NEXT: add a2, a2, a4
-; RV32I-NEXT: slli a4, a2, 16
-; RV32I-NEXT: add a2, a2, a4
-; RV32I-NEXT: srli a2, a2, 24
-; RV32I-NEXT: add a2, a2, a3
-; RV32I-NEXT: sw zero, 12(a0)
-; RV32I-NEXT: sw zero, 4(a0)
-; RV32I-NEXT: sw a2, 8(a0)
-; RV32I-NEXT: sw a1, 0(a0)
+; RV32I-NEXT: addi sp, sp, -32
+; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
+; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
+; RV32I-NEXT: lw s0, 8(a1)
+; RV32I-NEXT: lw s1, 12(a1)
+; RV32I-NEXT: lw a2, 0(a1)
+; RV32I-NEXT: lw a1, 4(a1)
+; RV32I-NEXT: mv s2, a0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: call __popcountdi2
+; RV32I-NEXT: mv s3, a0
+; RV32I-NEXT: mv s4, a1
+; RV32I-NEXT: mv a0, s0
+; RV32I-NEXT: mv a1, s1
+; RV32I-NEXT: call __popcountdi2
+; RV32I-NEXT: sw a1, 12(s2)
+; RV32I-NEXT: sw a0, 8(s2)
+; RV32I-NEXT: sw s4, 4(s2)
+; RV32I-NEXT: sw s3, 0(s2)
+; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
+; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: ctpop_v2i64:
diff --git a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
index dcba42db886ae..670568f50a6fe 100644
--- a/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-ctpop.ll
@@ -4,35 +4,21 @@
define arm_aapcs_vfpcc <2 x i64> @ctpop_2i64_t(<2 x i64> %src){
; CHECK-LABEL: ctpop_2i64_t:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: .save {r4, r5, r6, lr}
-; CHECK-NEXT: push {r4, r5, r6, lr}
+; CHECK-NEXT: .save {r4, r5, r7, lr}
+; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vmov q4, q0
-; CHECK-NEXT: vmov r4, r0, d9
-; CHECK-NEXT: bl __popcountsi2
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: bl __popcountsi2
-; CHECK-NEXT: vmov r4, r1, d8
-; CHECK-NEXT: adds r6, r0, r5
-; CHECK-NEXT: vldr s17, .LCPI0_0
-; CHECK-NEXT: mov r0, r1
-; CHECK-NEXT: bl __popcountsi2
-; CHECK-NEXT: mov r5, r0
-; CHECK-NEXT: mov r0, r4
-; CHECK-NEXT: vmov s18, r6
-; CHECK-NEXT: bl __popcountsi2
-; CHECK-NEXT: add r0, r5
-; CHECK-NEXT: vmov.f32 s19, s17
-; CHECK-NEXT: vmov s16, r0
-; CHECK-NEXT: vmov q0, q4
+; CHECK-NEXT: vmov r0, r1, d9
+; CHECK-NEXT: bl __popcountdi2
+; CHECK-NEXT: mov r4, r0
+; CHECK-NEXT: mov r5, r1
+; CHECK-NEXT: vmov r0, r1, d8
+; CHECK-NEXT: bl __popcountdi2
+; CHECK-NEXT: vmov q0[2], q0[0], r0, r4
+; CHECK-NEXT: vmov q0[3], q0[1], r1, r5
; CHECK-NEXT: vpop {d8, d9}
-; CHECK-NEXT: pop {r4, r5, r6, pc}
-; CHECK-NEXT: .p2align 2
-; CHECK-NEXT: @ %bb.1:
-; CHECK-NEXT: .LCPI0_0:
-; CHECK-NEXT: .long 0x00000000 @ float 0
+; CHECK-NEXT: pop {r4, r5, r7, pc}
entry:
%0 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %src)
ret <2 x i64> %0
>From 66ae5db5371cd4624d67bd2cbf39fb0f3c5722e4 Mon Sep 17 00:00:00 2001
From: Sergei Barannikov <barannikov88 at gmail.com>
Date: Sun, 21 Jul 2024 15:28:13 +0300
Subject: [PATCH 4/4] [RISCV] Expand 64-bit CTPOP into a libcall
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +
.../Analysis/CostModel/RISCV/int-bit-manip.ll | 16 +-
llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll | 330 +++---------------
.../CodeGen/RISCV/ctz_zero_return_test.ll | 36 +-
llvm/test/CodeGen/RISCV/pr56457.ll | 31 +-
.../RISCV/rv64-legal-i32/rv64xtheadbb.ll | 34 +-
.../CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll | 65 +---
llvm/test/CodeGen/RISCV/rv64xtheadbb.ll | 34 +-
llvm/test/CodeGen/RISCV/rv64zbb.ll | 126 ++-----
llvm/test/CodeGen/RISCV/sextw-removal.ll | 46 +--
10 files changed, 110 insertions(+), 610 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e938454b8e642..f774c4fdbda8f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -389,6 +389,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
} else if (!Subtarget.hasVendorXCVbitmanip()) {
setOperationAction({ISD::CTTZ, ISD::CTPOP}, XLenVT, Expand);
+ if (Subtarget.is64Bit())
+ setOperationAction(ISD::CTPOP, MVT::i64, LibCall);
if (RV64LegalI32 && Subtarget.is64Bit())
setOperationAction({ISD::CTTZ, ISD::CTPOP}, MVT::i32, Expand);
}
diff --git a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
index 380f65b19b8fa..c0ecc63b82dca 100644
--- a/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
+++ b/llvm/test/Analysis/CostModel/RISCV/int-bit-manip.ll
@@ -159,7 +159,7 @@ define void @bitreverse() {
define void @ctpop() {
; NOZVBB-LABEL: 'ctpop'
-; NOZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = call i8 @llvm.ctpop.i8(i8 undef)
+; NOZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call i8 @llvm.ctpop.i8(i8 undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %2 = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %3 = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %4 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> undef)
@@ -169,7 +169,7 @@ define void @ctpop() {
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %8 = call <vscale x 4 x i8> @llvm.ctpop.nxv4i8(<vscale x 4 x i8> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %9 = call <vscale x 8 x i8> @llvm.ctpop.nxv8i8(<vscale x 8 x i8> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %10 = call <vscale x 16 x i8> @llvm.ctpop.nxv16i8(<vscale x 16 x i8> undef)
-; NOZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call i16 @llvm.ctpop.i16(i16 undef)
+; NOZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = call i16 @llvm.ctpop.i16(i16 undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %12 = call <2 x i16> @llvm.ctpop.v2i16(<2 x i16> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %13 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %14 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> undef)
@@ -179,7 +179,7 @@ define void @ctpop() {
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %18 = call <vscale x 4 x i16> @llvm.ctpop.nxv4i16(<vscale x 4 x i16> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %19 = call <vscale x 8 x i16> @llvm.ctpop.nxv8i16(<vscale x 8 x i16> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 19 for instruction: %20 = call <vscale x 16 x i16> @llvm.ctpop.nxv16i16(<vscale x 16 x i16> undef)
-; NOZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %21 = call i32 @llvm.ctpop.i32(i32 undef)
+; NOZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %21 = call i32 @llvm.ctpop.i32(i32 undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %22 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %23 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %24 = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> undef)
@@ -189,7 +189,7 @@ define void @ctpop() {
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %28 = call <vscale x 4 x i32> @llvm.ctpop.nxv4i32(<vscale x 4 x i32> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %29 = call <vscale x 8 x i32> @llvm.ctpop.nxv8i32(<vscale x 8 x i32> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %30 = call <vscale x 16 x i32> @llvm.ctpop.nxv16i32(<vscale x 16 x i32> undef)
-; NOZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %31 = call i64 @llvm.ctpop.i64(i64 undef)
+; NOZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %31 = call i64 @llvm.ctpop.i64(i64 undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %32 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %33 = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> undef)
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 21 for instruction: %34 = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> undef)
@@ -202,7 +202,7 @@ define void @ctpop() {
; NOZVBB-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void
;
; ZVBB-LABEL: 'ctpop'
-; ZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %1 = call i8 @llvm.ctpop.i8(i8 undef)
+; ZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call i8 @llvm.ctpop.i8(i8 undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %2 = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %3 = call <4 x i8> @llvm.ctpop.v4i8(<4 x i8> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %4 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> undef)
@@ -212,7 +212,7 @@ define void @ctpop() {
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %8 = call <vscale x 4 x i8> @llvm.ctpop.nxv4i8(<vscale x 4 x i8> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %9 = call <vscale x 8 x i8> @llvm.ctpop.nxv8i8(<vscale x 8 x i8> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %10 = call <vscale x 16 x i8> @llvm.ctpop.nxv16i8(<vscale x 16 x i8> undef)
-; ZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %11 = call i16 @llvm.ctpop.i16(i16 undef)
+; ZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = call i16 @llvm.ctpop.i16(i16 undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %12 = call <2 x i16> @llvm.ctpop.v2i16(<2 x i16> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <4 x i16> @llvm.ctpop.v4i16(<4 x i16> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %14 = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> undef)
@@ -222,7 +222,7 @@ define void @ctpop() {
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %18 = call <vscale x 4 x i16> @llvm.ctpop.nxv4i16(<vscale x 4 x i16> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %19 = call <vscale x 8 x i16> @llvm.ctpop.nxv8i16(<vscale x 8 x i16> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %20 = call <vscale x 16 x i16> @llvm.ctpop.nxv16i16(<vscale x 16 x i16> undef)
-; ZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %21 = call i32 @llvm.ctpop.i32(i32 undef)
+; ZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %21 = call i32 @llvm.ctpop.i32(i32 undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %22 = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %23 = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %24 = call <8 x i32> @llvm.ctpop.v8i32(<8 x i32> undef)
@@ -232,7 +232,7 @@ define void @ctpop() {
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %28 = call <vscale x 4 x i32> @llvm.ctpop.nxv4i32(<vscale x 4 x i32> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %29 = call <vscale x 8 x i32> @llvm.ctpop.nxv8i32(<vscale x 8 x i32> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %30 = call <vscale x 16 x i32> @llvm.ctpop.nxv16i32(<vscale x 16 x i32> undef)
-; ZVBB-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %31 = call i64 @llvm.ctpop.i64(i64 undef)
+; ZVBB-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %31 = call i64 @llvm.ctpop.i64(i64 undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %32 = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %33 = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> undef)
; ZVBB-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %34 = call <8 x i64> @llvm.ctpop.v8i64(<8 x i64> undef)
diff --git a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
index 24100654467f4..120f7d9dd2568 100644
--- a/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
+++ b/llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
@@ -1415,56 +1415,32 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: test_ctlz_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: beqz a0, .LBB11_2
-; RV64I-NEXT: # %bb.1: # %cond.false
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ret
-; RV64I-NEXT: .LBB11_2:
-; RV64I-NEXT: li a0, 64
-; RV64I-NEXT: ret
+; RV64NOZBB-LABEL: test_ctlz_i64:
+; RV64NOZBB: # %bb.0:
+; RV64NOZBB-NEXT: beqz a0, .LBB11_2
+; RV64NOZBB-NEXT: # %bb.1: # %cond.false
+; RV64NOZBB-NEXT: addi sp, sp, -16
+; RV64NOZBB-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
+; RV64NOZBB-NEXT: srli a1, a0, 1
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 2
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 4
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 8
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 16
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 32
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: not a0, a0
+; RV64NOZBB-NEXT: call __popcountdi2
+; RV64NOZBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64NOZBB-NEXT: addi sp, sp, 16
+; RV64NOZBB-NEXT: ret
+; RV64NOZBB-NEXT: .LBB11_2:
+; RV64NOZBB-NEXT: li a0, 64
+; RV64NOZBB-NEXT: ret
;
; RV32M-LABEL: test_ctlz_i64:
; RV32M: # %bb.0:
@@ -1531,56 +1507,6 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV32M-NEXT: li a1, 0
; RV32M-NEXT: ret
;
-; RV64M-LABEL: test_ctlz_i64:
-; RV64M: # %bb.0:
-; RV64M-NEXT: beqz a0, .LBB11_2
-; RV64M-NEXT: # %bb.1: # %cond.false
-; RV64M-NEXT: srli a1, a0, 1
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 2
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 4
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 8
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 16
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 32
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: not a0, a0
-; RV64M-NEXT: srli a1, a0, 1
-; RV64M-NEXT: lui a2, 349525
-; RV64M-NEXT: addiw a2, a2, 1365
-; RV64M-NEXT: slli a3, a2, 32
-; RV64M-NEXT: add a2, a2, a3
-; RV64M-NEXT: and a1, a1, a2
-; RV64M-NEXT: sub a0, a0, a1
-; RV64M-NEXT: lui a1, 209715
-; RV64M-NEXT: addiw a1, a1, 819
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: and a2, a0, a1
-; RV64M-NEXT: srli a0, a0, 2
-; RV64M-NEXT: and a0, a0, a1
-; RV64M-NEXT: add a0, a2, a0
-; RV64M-NEXT: srli a1, a0, 4
-; RV64M-NEXT: add a0, a0, a1
-; RV64M-NEXT: lui a1, 61681
-; RV64M-NEXT: addiw a1, a1, -241
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: and a0, a0, a1
-; RV64M-NEXT: lui a1, 4112
-; RV64M-NEXT: addiw a1, a1, 257
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: mul a0, a0, a1
-; RV64M-NEXT: srli a0, a0, 56
-; RV64M-NEXT: ret
-; RV64M-NEXT: .LBB11_2:
-; RV64M-NEXT: li a0, 64
-; RV64M-NEXT: ret
-;
; RV32ZBB-LABEL: test_ctlz_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a1, .LBB11_2
@@ -2030,51 +1956,22 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
-; RV64I-LABEL: test_ctlz_i64_zero_undef:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 2
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 8
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 16
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: srli a1, a0, 32
-; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ret
+; RV64NOZBB-LABEL: test_ctlz_i64_zero_undef:
+; RV64NOZBB: # %bb.0:
+; RV64NOZBB-NEXT: srli a1, a0, 1
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 2
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 4
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 8
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 16
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: srli a1, a0, 32
+; RV64NOZBB-NEXT: or a0, a0, a1
+; RV64NOZBB-NEXT: not a0, a0
+; RV64NOZBB-NEXT: tail __popcountdi2
;
; RV32M-LABEL: test_ctlz_i64_zero_undef:
; RV32M: # %bb.0:
@@ -2141,51 +2038,6 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32M-NEXT: li a1, 0
; RV32M-NEXT: ret
;
-; RV64M-LABEL: test_ctlz_i64_zero_undef:
-; RV64M: # %bb.0:
-; RV64M-NEXT: srli a1, a0, 1
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 2
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 4
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 8
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 16
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: srli a1, a0, 32
-; RV64M-NEXT: or a0, a0, a1
-; RV64M-NEXT: not a0, a0
-; RV64M-NEXT: srli a1, a0, 1
-; RV64M-NEXT: lui a2, 349525
-; RV64M-NEXT: addiw a2, a2, 1365
-; RV64M-NEXT: slli a3, a2, 32
-; RV64M-NEXT: add a2, a2, a3
-; RV64M-NEXT: and a1, a1, a2
-; RV64M-NEXT: sub a0, a0, a1
-; RV64M-NEXT: lui a1, 209715
-; RV64M-NEXT: addiw a1, a1, 819
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: and a2, a0, a1
-; RV64M-NEXT: srli a0, a0, 2
-; RV64M-NEXT: and a0, a0, a1
-; RV64M-NEXT: add a0, a2, a0
-; RV64M-NEXT: srli a1, a0, 4
-; RV64M-NEXT: add a0, a0, a1
-; RV64M-NEXT: lui a1, 61681
-; RV64M-NEXT: addiw a1, a1, -241
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: and a0, a0, a1
-; RV64M-NEXT: lui a1, 4112
-; RV64M-NEXT: addiw a1, a1, 257
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: mul a0, a0, a1
-; RV64M-NEXT: srli a0, a0, 56
-; RV64M-NEXT: ret
-;
; RV32ZBB-LABEL: test_ctlz_i64_zero_undef:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: bnez a1, .LBB15_2
@@ -2569,70 +2421,9 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32_NOZBB-NEXT: addi sp, sp, 16
; RV32_NOZBB-NEXT: ret
;
-; RV64I-LABEL: test_ctpop_i64:
-; RV64I: # %bb.0:
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ret
-;
-; RV64M-LABEL: test_ctpop_i64:
-; RV64M: # %bb.0:
-; RV64M-NEXT: srli a1, a0, 1
-; RV64M-NEXT: lui a2, 349525
-; RV64M-NEXT: addiw a2, a2, 1365
-; RV64M-NEXT: slli a3, a2, 32
-; RV64M-NEXT: add a2, a2, a3
-; RV64M-NEXT: and a1, a1, a2
-; RV64M-NEXT: sub a0, a0, a1
-; RV64M-NEXT: lui a1, 209715
-; RV64M-NEXT: addiw a1, a1, 819
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: and a2, a0, a1
-; RV64M-NEXT: srli a0, a0, 2
-; RV64M-NEXT: and a0, a0, a1
-; RV64M-NEXT: add a0, a2, a0
-; RV64M-NEXT: srli a1, a0, 4
-; RV64M-NEXT: add a0, a0, a1
-; RV64M-NEXT: lui a1, 61681
-; RV64M-NEXT: addiw a1, a1, -241
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: and a0, a0, a1
-; RV64M-NEXT: lui a1, 4112
-; RV64M-NEXT: addiw a1, a1, 257
-; RV64M-NEXT: slli a2, a1, 32
-; RV64M-NEXT: add a1, a1, a2
-; RV64M-NEXT: mul a0, a0, a1
-; RV64M-NEXT: srli a0, a0, 56
-; RV64M-NEXT: ret
+; RV64NOZBB-LABEL: test_ctpop_i64:
+; RV64NOZBB: # %bb.0:
+; RV64NOZBB-NEXT: tail __popcountdi2
;
; RV32ZBB-LABEL: test_ctpop_i64:
; RV32ZBB: # %bb.0:
@@ -2658,36 +2449,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
;
; RV64XTHEADBB-LABEL: test_ctpop_i64:
; RV64XTHEADBB: # %bb.0:
-; RV64XTHEADBB-NEXT: srli a1, a0, 1
-; RV64XTHEADBB-NEXT: lui a2, 349525
-; RV64XTHEADBB-NEXT: addiw a2, a2, 1365
-; RV64XTHEADBB-NEXT: slli a3, a2, 32
-; RV64XTHEADBB-NEXT: add a2, a2, a3
-; RV64XTHEADBB-NEXT: and a1, a1, a2
-; RV64XTHEADBB-NEXT: sub a0, a0, a1
-; RV64XTHEADBB-NEXT: lui a1, 209715
-; RV64XTHEADBB-NEXT: addiw a1, a1, 819
-; RV64XTHEADBB-NEXT: slli a2, a1, 32
-; RV64XTHEADBB-NEXT: add a1, a1, a2
-; RV64XTHEADBB-NEXT: and a2, a0, a1
-; RV64XTHEADBB-NEXT: srli a0, a0, 2
-; RV64XTHEADBB-NEXT: and a0, a0, a1
-; RV64XTHEADBB-NEXT: add a0, a2, a0
-; RV64XTHEADBB-NEXT: srli a1, a0, 4
-; RV64XTHEADBB-NEXT: add a0, a0, a1
-; RV64XTHEADBB-NEXT: lui a1, 61681
-; RV64XTHEADBB-NEXT: addiw a1, a1, -241
-; RV64XTHEADBB-NEXT: slli a2, a1, 32
-; RV64XTHEADBB-NEXT: add a1, a1, a2
-; RV64XTHEADBB-NEXT: and a0, a0, a1
-; RV64XTHEADBB-NEXT: slli a1, a0, 8
-; RV64XTHEADBB-NEXT: add a0, a0, a1
-; RV64XTHEADBB-NEXT: slli a1, a0, 16
-; RV64XTHEADBB-NEXT: add a0, a0, a1
-; RV64XTHEADBB-NEXT: slli a1, a0, 32
-; RV64XTHEADBB-NEXT: add a0, a0, a1
-; RV64XTHEADBB-NEXT: srli a0, a0, 56
-; RV64XTHEADBB-NEXT: ret
+; RV64XTHEADBB-NEXT: tail __popcountdi2
%1 = call i64 @llvm.ctpop.i64(i64 %a)
ret i64 %1
}
diff --git a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
index fe6e20d852d59..f45c1632814c9 100644
--- a/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
+++ b/llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
@@ -671,6 +671,8 @@ define signext i32 @ctlz(i64 %b) nounwind {
;
; RV64I-LABEL: ctlz:
; RV64I: # %bb.0: # %entry
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2
@@ -684,36 +686,10 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a0, a0, 2
-; RV64I-NEXT: srli a0, a0, 58
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: andi a0, a0, 63
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/pr56457.ll b/llvm/test/CodeGen/RISCV/pr56457.ll
index ba08aa838bf99..19cc8b3af208f 100644
--- a/llvm/test/CodeGen/RISCV/pr56457.ll
+++ b/llvm/test/CodeGen/RISCV/pr56457.ll
@@ -9,6 +9,8 @@ define i15 @foo(i15 %x) nounwind {
; CHECK-NEXT: slli a1, a0, 49
; CHECK-NEXT: beqz a1, .LBB0_2
; CHECK-NEXT: # %bb.1: # %cond.false
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: srli a1, a1, 50
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: slli a1, a0, 49
@@ -21,34 +23,11 @@ define i15 @foo(i15 %x) nounwind {
; CHECK-NEXT: srli a1, a1, 57
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: not a0, a0
-; CHECK-NEXT: srli a1, a0, 1
-; CHECK-NEXT: lui a2, 1
-; CHECK-NEXT: addiw a2, a2, 1365
-; CHECK-NEXT: and a1, a1, a2
; CHECK-NEXT: slli a0, a0, 49
; CHECK-NEXT: srli a0, a0, 49
-; CHECK-NEXT: sub a0, a0, a1
-; CHECK-NEXT: lui a1, 209715
-; CHECK-NEXT: addiw a1, a1, 819
-; CHECK-NEXT: slli a2, a1, 32
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: and a2, a0, a1
-; CHECK-NEXT: srli a0, a0, 2
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: add a0, a2, a0
-; CHECK-NEXT: srli a1, a0, 4
-; CHECK-NEXT: add a0, a0, a1
-; CHECK-NEXT: lui a1, 61681
-; CHECK-NEXT: addiw a1, a1, -241
-; CHECK-NEXT: slli a2, a1, 32
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: and a0, a0, a1
-; CHECK-NEXT: lui a1, 4112
-; CHECK-NEXT: addiw a1, a1, 257
-; CHECK-NEXT: slli a2, a1, 32
-; CHECK-NEXT: add a1, a1, a2
-; CHECK-NEXT: mul a0, a0, a1
-; CHECK-NEXT: srli a0, a0, 56
+; CHECK-NEXT: call __popcountdi2
+; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: li a0, 15
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
index 80d3add385969..eb8b5c9dd695f 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64xtheadbb.ll
@@ -317,6 +317,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %cond.false
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2
@@ -330,35 +332,9 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: li a0, 64
diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
index b0e447b71178b..445b4dc671296 100644
--- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
@@ -307,6 +307,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %cond.false
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2
@@ -320,35 +322,9 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: li a0, 64
@@ -620,36 +596,7 @@ declare i64 @llvm.ctpop.i64(i64)
define i64 @ctpop_i64(i64 %a) nounwind {
; RV64I-LABEL: ctpop_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ret
+; RV64I-NEXT: tail __popcountdi2
;
; RV64ZBB-LABEL: ctpop_i64:
; RV64ZBB: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
index 6cdab888ffcde..c667b930c1ee0 100644
--- a/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
@@ -295,6 +295,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %cond.false
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2
@@ -308,35 +310,9 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: li a0, 64
diff --git a/llvm/test/CodeGen/RISCV/rv64zbb.ll b/llvm/test/CodeGen/RISCV/rv64zbb.ll
index 6c354cc1b446b..d331a85589fca 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbb.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbb.ll
@@ -285,6 +285,8 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: beqz a0, .LBB5_2
; RV64I-NEXT: # %bb.1: # %cond.false
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2
@@ -298,35 +300,9 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: li a0, 64
@@ -828,36 +804,7 @@ declare i64 @llvm.ctpop.i64(i64)
define i64 @ctpop_i64(i64 %a) nounwind {
; RV64I-LABEL: ctpop_i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: lui a2, 349525
-; RV64I-NEXT: addiw a2, a2, 1365
-; RV64I-NEXT: slli a3, a2, 32
-; RV64I-NEXT: add a2, a2, a3
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw a1, a1, 819
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a2, a0, a1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: add a0, a2, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw a1, a1, -241
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 8
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 16
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: slli a1, a0, 32
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: ret
+; RV64I-NEXT: tail __popcountdi2
;
; RV64ZBB-LABEL: ctpop_i64:
; RV64ZBB: # %bb.0:
@@ -948,52 +895,21 @@ declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>)
define <2 x i64> @ctpop_v2i64(<2 x i64> %a) nounwind {
; RV64I-LABEL: ctpop_v2i64:
; RV64I: # %bb.0:
-; RV64I-NEXT: srli a2, a0, 1
-; RV64I-NEXT: lui a3, 349525
-; RV64I-NEXT: addiw a3, a3, 1365
-; RV64I-NEXT: slli a4, a3, 32
-; RV64I-NEXT: add a3, a3, a4
-; RV64I-NEXT: and a2, a2, a3
-; RV64I-NEXT: sub a0, a0, a2
-; RV64I-NEXT: lui a2, 209715
-; RV64I-NEXT: addiw a2, a2, 819
-; RV64I-NEXT: slli a4, a2, 32
-; RV64I-NEXT: add a2, a2, a4
-; RV64I-NEXT: and a4, a0, a2
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, a2
-; RV64I-NEXT: add a0, a4, a0
-; RV64I-NEXT: srli a4, a0, 4
-; RV64I-NEXT: add a0, a0, a4
-; RV64I-NEXT: lui a4, 61681
-; RV64I-NEXT: addiw a4, a4, -241
-; RV64I-NEXT: slli a5, a4, 32
-; RV64I-NEXT: add a4, a4, a5
-; RV64I-NEXT: and a0, a0, a4
-; RV64I-NEXT: slli a5, a0, 8
-; RV64I-NEXT: add a0, a0, a5
-; RV64I-NEXT: slli a5, a0, 16
-; RV64I-NEXT: add a0, a0, a5
-; RV64I-NEXT: slli a5, a0, 32
-; RV64I-NEXT: add a0, a0, a5
-; RV64I-NEXT: srli a0, a0, 56
-; RV64I-NEXT: srli a5, a1, 1
-; RV64I-NEXT: and a3, a5, a3
-; RV64I-NEXT: sub a1, a1, a3
-; RV64I-NEXT: and a3, a1, a2
-; RV64I-NEXT: srli a1, a1, 2
-; RV64I-NEXT: and a1, a1, a2
-; RV64I-NEXT: add a1, a3, a1
-; RV64I-NEXT: srli a2, a1, 4
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: and a1, a1, a4
-; RV64I-NEXT: slli a2, a1, 8
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a1, 16
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: slli a2, a1, 32
-; RV64I-NEXT: add a1, a1, a2
-; RV64I-NEXT: srli a1, a1, 56
+; RV64I-NEXT: addi sp, sp, -32
+; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
+; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: mv s0, a1
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: mv s1, a0
+; RV64I-NEXT: mv a0, s0
+; RV64I-NEXT: call __popcountdi2
+; RV64I-NEXT: mv a1, a0
+; RV64I-NEXT: mv a0, s1
+; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
+; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: ctpop_v2i64:
diff --git a/llvm/test/CodeGen/RISCV/sextw-removal.ll b/llvm/test/CodeGen/RISCV/sextw-removal.ll
index 8cf78551d28f9..f9a2c543d5410 100644
--- a/llvm/test/CodeGen/RISCV/sextw-removal.ll
+++ b/llvm/test/CodeGen/RISCV/sextw-removal.ll
@@ -316,52 +316,18 @@ declare float @baz(i32 signext %i3)
define void @test7(i32 signext %arg, i32 signext %arg1) nounwind {
; RV64I-LABEL: test7:
; RV64I: # %bb.0: # %bb
-; RV64I-NEXT: addi sp, sp, -48
-; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
-; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
+; RV64I-NEXT: addi sp, sp, -16
+; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: lui a1, 349525
-; RV64I-NEXT: addiw s0, a1, 1365
-; RV64I-NEXT: slli a1, s0, 32
-; RV64I-NEXT: add s0, s0, a1
-; RV64I-NEXT: lui a1, 209715
-; RV64I-NEXT: addiw s1, a1, 819
-; RV64I-NEXT: slli a1, s1, 32
-; RV64I-NEXT: add s1, s1, a1
-; RV64I-NEXT: lui a1, 61681
-; RV64I-NEXT: addiw s2, a1, -241
-; RV64I-NEXT: slli a1, s2, 32
-; RV64I-NEXT: add s2, s2, a1
-; RV64I-NEXT: lui a1, 4112
-; RV64I-NEXT: addiw s3, a1, 257
-; RV64I-NEXT: slli a1, s3, 32
-; RV64I-NEXT: add s3, s3, a1
; RV64I-NEXT: .LBB6_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
+; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: call foo
-; RV64I-NEXT: srli a1, a0, 1
-; RV64I-NEXT: and a1, a1, s0
-; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: and a1, a0, s1
-; RV64I-NEXT: srli a0, a0, 2
-; RV64I-NEXT: and a0, a0, s1
-; RV64I-NEXT: add a0, a1, a0
-; RV64I-NEXT: srli a1, a0, 4
-; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: and a0, a0, s2
-; RV64I-NEXT: mul a0, a0, s3
-; RV64I-NEXT: srli a0, a0, 56
+; RV64I-NEXT: call __popcountdi2
; RV64I-NEXT: bnez a0, .LBB6_1
; RV64I-NEXT: # %bb.2: # %bb7
-; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
-; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
-; RV64I-NEXT: addi sp, sp, 48
+; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: test7:
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