[llvm] Revert "[LoongArch] Remove spurious mask operations from andn->icmp on 16 and 8 bit values" (PR #99792)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 20 18:31:25 PDT 2024
https://github.com/heiher created https://github.com/llvm/llvm-project/pull/99792
Reverts llvm/llvm-project#99272
>From 3deacfb6a58ea3dcae27807209dffb227e9c786c Mon Sep 17 00:00:00 2001
From: hev <r at hev.cc>
Date: Sun, 21 Jul 2024 09:30:48 +0800
Subject: [PATCH] =?UTF-8?q?Revert=20"[LoongArch]=20Remove=20spurious=20mas?=
=?UTF-8?q?k=20operations=20from=20andn->icmp=20on=2016=20and=E2=80=A6"?=
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This reverts commit c41fa0fdd7e14019fc48bece2a2b0b00c88c8518.
---
.../LoongArch/LoongArchISelLowering.cpp | 162 ------------------
llvm/test/CodeGen/LoongArch/andn-icmp.ll | 56 ++++--
2 files changed, 40 insertions(+), 178 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 6072e5e244263..ba6be85c7f2e8 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -335,7 +335,6 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setTargetDAGCombine(ISD::AND);
setTargetDAGCombine(ISD::OR);
setTargetDAGCombine(ISD::SRL);
- setTargetDAGCombine(ISD::SETCC);
// Set DAG combine for 'LSX' feature.
@@ -2529,165 +2528,6 @@ static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
return SDValue();
}
-static bool checkValueWidth(SDValue V, ISD::LoadExtType &ExtType) {
- ExtType = ISD::NON_EXTLOAD;
-
- switch (V.getNode()->getOpcode()) {
- case ISD::LOAD: {
- LoadSDNode *LoadNode = cast<LoadSDNode>(V.getNode());
- if ((LoadNode->getMemoryVT() == MVT::i8) ||
- (LoadNode->getMemoryVT() == MVT::i16)) {
- ExtType = LoadNode->getExtensionType();
- return true;
- }
- return false;
- }
- case ISD::AssertSext: {
- VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
- if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) {
- ExtType = ISD::SEXTLOAD;
- return true;
- }
- return false;
- }
- case ISD::AssertZext: {
- VTSDNode *TypeNode = cast<VTSDNode>(V.getNode()->getOperand(1));
- if ((TypeNode->getVT() == MVT::i8) || (TypeNode->getVT() == MVT::i16)) {
- ExtType = ISD::ZEXTLOAD;
- return true;
- }
- return false;
- }
- default:
- return false;
- }
-
- return false;
-}
-
-// Eliminate redundant truncation and zero-extension nodes.
-// * Case 1:
-// +------------+ +------------+ +------------+
-// | Input1 | | Input2 | | CC |
-// +------------+ +------------+ +------------+
-// | | |
-// V V +----+
-// +------------+ +------------+ |
-// | TRUNCATE | | TRUNCATE | |
-// +------------+ +------------+ |
-// | | |
-// V V |
-// +------------+ +------------+ |
-// | ZERO_EXT | | ZERO_EXT | |
-// +------------+ +------------+ |
-// | | |
-// | +-------------+ |
-// V V | |
-// +----------------+ | |
-// | AND | | |
-// +----------------+ | |
-// | | |
-// +---------------+ | |
-// | | |
-// V V V
-// +-------------+
-// | CMP |
-// +-------------+
-// * Case 2:
-// +------------+ +------------+ +-------------+ +------------+ +------------+
-// | Input1 | | Input2 | | Constant -1 | | Constant 0 | | CC |
-// +------------+ +------------+ +-------------+ +------------+ +------------+
-// | | | | |
-// V | | | |
-// +------------+ | | | |
-// | XOR |<---------------------+ | |
-// +------------+ | | |
-// | | | |
-// V V +---------------+ |
-// +------------+ +------------+ | |
-// | TRUNCATE | | TRUNCATE | | +-------------------------+
-// +------------+ +------------+ | |
-// | | | |
-// V V | |
-// +------------+ +------------+ | |
-// | ZERO_EXT | | ZERO_EXT | | |
-// +------------+ +------------+ | |
-// | | | |
-// V V | |
-// +----------------+ | |
-// | AND | | |
-// +----------------+ | |
-// | | |
-// +---------------+ | |
-// | | |
-// V V V
-// +-------------+
-// | CMP |
-// +-------------+
-static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG,
- TargetLowering::DAGCombinerInfo &DCI,
- const LoongArchSubtarget &Subtarget) {
- ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
-
- SDNode *AndNode = N->getOperand(0).getNode();
- if (AndNode->getOpcode() != ISD::AND)
- return SDValue();
-
- SDValue AndInputValue2 = AndNode->getOperand(1);
- if (AndInputValue2.getOpcode() != ISD::ZERO_EXTEND)
- return SDValue();
-
- SDValue CmpInputValue = N->getOperand(1);
- SDValue AndInputValue1 = AndNode->getOperand(0);
- if (AndInputValue1.getOpcode() == ISD::XOR) {
- if (CC != ISD::SETEQ && CC != ISD::SETNE)
- return SDValue();
- ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndInputValue1.getOperand(1));
- if (!CN || CN->getSExtValue() != -1)
- return SDValue();
- CN = dyn_cast<ConstantSDNode>(CmpInputValue);
- if (!CN || CN->getSExtValue() != 0)
- return SDValue();
- AndInputValue1 = AndInputValue1.getOperand(0);
- if (AndInputValue1.getOpcode() != ISD::ZERO_EXTEND)
- return SDValue();
- } else if (AndInputValue1.getOpcode() == ISD::ZERO_EXTEND) {
- if (AndInputValue2 != CmpInputValue)
- return SDValue();
- } else {
- return SDValue();
- }
-
- SDValue TruncValue1 = AndInputValue1.getNode()->getOperand(0);
- if (TruncValue1.getOpcode() != ISD::TRUNCATE)
- return SDValue();
-
- SDValue TruncValue2 = AndInputValue2.getNode()->getOperand(0);
- if (TruncValue2.getOpcode() != ISD::TRUNCATE)
- return SDValue();
-
- SDValue TruncInputValue1 = TruncValue1.getNode()->getOperand(0);
- SDValue TruncInputValue2 = TruncValue2.getNode()->getOperand(0);
- ISD::LoadExtType ExtType1;
- ISD::LoadExtType ExtType2;
-
- if (!checkValueWidth(TruncInputValue1, ExtType1) ||
- !checkValueWidth(TruncInputValue2, ExtType2))
- return SDValue();
-
- if ((ExtType2 != ISD::ZEXTLOAD) &&
- ((ExtType2 != ISD::SEXTLOAD) && (ExtType1 != ISD::SEXTLOAD)))
- return SDValue();
-
- // These truncation and zero-extension nodes are not necessary, remove them.
- SDValue NewAnd = DAG.getNode(ISD::AND, SDLoc(N), AndNode->getValueType(0),
- TruncInputValue1, TruncInputValue2);
- SDValue NewSetCC =
- DAG.getSetCC(SDLoc(N), N->getValueType(0), NewAnd, TruncInputValue2, CC);
- DAG.ReplaceAllUsesWith(N, NewSetCC.getNode());
- return SDValue(N, 0);
-}
-
// Combine (loongarch_bitrev_w (loongarch_revb_2w X)) to loongarch_bitrev_4b.
static SDValue performBITREV_WCombine(SDNode *N, SelectionDAG &DAG,
TargetLowering::DAGCombinerInfo &DCI,
@@ -3315,8 +3155,6 @@ SDValue LoongArchTargetLowering::PerformDAGCombine(SDNode *N,
return performANDCombine(N, DAG, DCI, Subtarget);
case ISD::OR:
return performORCombine(N, DAG, DCI, Subtarget);
- case ISD::SETCC:
- return performSETCCCombine(N, DAG, DCI, Subtarget);
case ISD::SRL:
return performSRLCombine(N, DAG, DCI, Subtarget);
case LoongArchISD::BITREV_W:
diff --git a/llvm/test/CodeGen/LoongArch/andn-icmp.ll b/llvm/test/CodeGen/LoongArch/andn-icmp.ll
index 6d07e7a947297..4fc3c8df4664c 100644
--- a/llvm/test/CodeGen/LoongArch/andn-icmp.ll
+++ b/llvm/test/CodeGen/LoongArch/andn-icmp.ll
@@ -6,12 +6,14 @@ define i1 @andn_icmp_eq_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_eq_i8:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
+; LA32-NEXT: andi $a0, $a0, 255
; LA32-NEXT: sltui $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_eq_i8:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
+; LA64-NEXT: andi $a0, $a0, 255
; LA64-NEXT: sltui $a0, $a0, 1
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -23,12 +25,14 @@ define i1 @andn_icmp_eq_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_eq_i16:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
+; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
; LA32-NEXT: sltui $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_eq_i16:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
+; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
; LA64-NEXT: sltui $a0, $a0, 1
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -76,12 +80,14 @@ define i1 @andn_icmp_ne_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ne_i8:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
+; LA32-NEXT: andi $a0, $a0, 255
; LA32-NEXT: sltu $a0, $zero, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ne_i8:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
+; LA64-NEXT: andi $a0, $a0, 255
; LA64-NEXT: sltu $a0, $zero, $a0
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -93,12 +99,14 @@ define i1 @andn_icmp_ne_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ne_i16:
; LA32: # %bb.0:
; LA32-NEXT: andn $a0, $a1, $a0
+; LA32-NEXT: bstrpick.w $a0, $a0, 15, 0
; LA32-NEXT: sltu $a0, $zero, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ne_i16:
; LA64: # %bb.0:
; LA64-NEXT: andn $a0, $a1, $a0
+; LA64-NEXT: bstrpick.d $a0, $a0, 15, 0
; LA64-NEXT: sltu $a0, $zero, $a0
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -145,13 +153,15 @@ define i1 @andn_icmp_ne_i64(i64 %a, i64 %b) nounwind {
define i1 @andn_icmp_ult_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ult_i8:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: andi $a1, $a1, 255
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ult_i8:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: andi $a1, $a1, 255
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -162,13 +172,15 @@ define i1 @andn_icmp_ult_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_ult_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ult_i16:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ult_i16:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -179,14 +191,16 @@ define i1 @andn_icmp_ult_i16(i16 signext %a, i16 signext %b) nounwind {
define i1 @andn_icmp_uge_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_uge_i8:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: andi $a1, $a1, 255
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_uge_i8:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: andi $a1, $a1, 255
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
@@ -198,14 +212,16 @@ define i1 @andn_icmp_uge_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_uge_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_uge_i16:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a0, $a1
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_uge_i16:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a0, $a1
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
@@ -217,13 +233,15 @@ define i1 @andn_icmp_uge_i16(i16 signext %a, i16 signext %b) nounwind {
define i1 @andn_icmp_ugt_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ugt_i8:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: andi $a1, $a1, 255
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ugt_i8:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: andi $a1, $a1, 255
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: ret
%and = and i8 %a, %b
@@ -234,13 +252,15 @@ define i1 @andn_icmp_ugt_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_ugt_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ugt_i16:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ugt_i16:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: ret
%and = and i16 %a, %b
@@ -251,14 +271,16 @@ define i1 @andn_icmp_ugt_i16(i16 signext %a, i16 signext %b) nounwind {
define i1 @andn_icmp_ule_i8(i8 signext %a, i8 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ule_i8:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: andi $a1, $a1, 255
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ule_i8:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: andi $a1, $a1, 255
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
@@ -270,14 +292,16 @@ define i1 @andn_icmp_ule_i8(i8 signext %a, i8 signext %b) nounwind {
define i1 @andn_icmp_ule_i16(i16 signext %a, i16 signext %b) nounwind {
; LA32-LABEL: andn_icmp_ule_i16:
; LA32: # %bb.0:
-; LA32-NEXT: and $a0, $a0, $a1
+; LA32-NEXT: bstrpick.w $a1, $a1, 15, 0
+; LA32-NEXT: and $a0, $a1, $a0
; LA32-NEXT: sltu $a0, $a1, $a0
; LA32-NEXT: xori $a0, $a0, 1
; LA32-NEXT: ret
;
; LA64-LABEL: andn_icmp_ule_i16:
; LA64: # %bb.0:
-; LA64-NEXT: and $a0, $a0, $a1
+; LA64-NEXT: bstrpick.d $a1, $a1, 15, 0
+; LA64-NEXT: and $a0, $a1, $a0
; LA64-NEXT: sltu $a0, $a1, $a0
; LA64-NEXT: xori $a0, $a0, 1
; LA64-NEXT: ret
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