[llvm] [PowerPC] Utilize `getReservedRegs` to find asm clobberable registers. (PR #99766)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Jul 20 08:17:38 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Esme (EsmeYi)
<details>
<summary>Changes</summary>
This patch utilizes `getReservedRegs()` to find asm clobberable registers.
And to make the result of `getReservedRegs()` accurate, this patch implements the todo, which is to make r2 allocatable on AIX for some leaf functions.
---
Patch is 32.40 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/99766.diff
13 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPCFrameLowering.cpp (+1-1)
- (modified) llvm/lib/Target/PowerPC/PPCISelLowering.cpp (+2)
- (modified) llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp (+13-15)
- (modified) llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll (+7-7)
- (modified) llvm/test/CodeGen/PowerPC/aix-cc-abi.ll (+4-4)
- (added) llvm/test/CodeGen/PowerPC/aix-inline-asm-clobber-warning.ll (+13)
- (modified) llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir (+2-3)
- (modified) llvm/test/CodeGen/PowerPC/inc-of-add.ll (+63-63)
- (modified) llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll (+23-2)
- (modified) llvm/test/CodeGen/PowerPC/ldst-16-byte.mir (+33-37)
- (modified) llvm/test/CodeGen/PowerPC/mflr-store.mir (+2-2)
- (modified) llvm/test/CodeGen/PowerPC/peephole-replaceInstr-after-eliminate-extsw.mir (+7-4)
- (modified) llvm/test/CodeGen/PowerPC/tocdata-non-zero-addend.mir (+2)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
index 277d708013c78..a0dbd480a413b 100644
--- a/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFrameLowering.cpp
@@ -2762,7 +2762,7 @@ void PPCFrameLowering::updateCalleeSaves(const MachineFunction &MF,
// Get the lowest numbered register for each class that actually needs
// to be saved.
MCPhysReg Cand = CSRegs[i];
- if (!SavedRegs.test(Cand))
+ if (!SavedRegs.test(Cand) || Cand == PPC::X2)
continue;
if (PPC::GPRCRegClass.contains(Cand) && Cand < LowestGPR)
LowestGPR = Cand;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4d4008ac0ba70..f9771bea613a5 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3432,6 +3432,8 @@ SDValue PPCTargetLowering::LowerGlobalTLSAddressAIX(SDValue Op,
if (Subtarget.hasAIXShLibTLSModelOpt())
updateForAIXShLibTLSModelOpt(Model, DAG, getTargetMachine());
+ setUsesTOCBasePtr(DAG);
+
bool IsTLSLocalExecModel = Model == TLSModel::LocalExec;
if (IsTLSLocalExecModel || Model == TLSModel::InitialExec) {
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 9e8da59615dfb..2df7a3b345db2 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -380,6 +380,8 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
markSuperRegs(Reserved, PPC::VRSAVE);
+ const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
+ bool UsesTOCBasePtr = FuncInfo->usesTOCBasePtr();
// The SVR4 ABI reserves r2 and r13
if (Subtarget.isSVR4ABI()) {
// We only reserve r2 if we need to use the TOC pointer. If we have no
@@ -387,16 +389,15 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
// no constant-pool loads, etc.) and we have no potential uses inside an
// inline asm block, then we can treat r2 has an ordinary callee-saved
// register.
- const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
- if (!TM.isPPC64() || FuncInfo->usesTOCBasePtr() || MF.hasInlineAsm())
- markSuperRegs(Reserved, PPC::R2); // System-reserved register
- markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register
+ if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
+ markSuperRegs(Reserved, PPC::R2); // System-reserved register.
+ markSuperRegs(Reserved, PPC::R13); // Small Data Area pointer register.
}
- // Always reserve r2 on AIX for now.
- // TODO: Make r2 allocatable on AIX/XCOFF for some leaf functions.
if (Subtarget.isAIXABI())
- markSuperRegs(Reserved, PPC::R2); // System-reserved register
+ // We only reserve r2 if we need to use the TOC pointer on AIX.
+ if (!TM.isPPC64() || UsesTOCBasePtr || MF.hasInlineAsm())
+ markSuperRegs(Reserved, PPC::R2); // System-reserved register.
// On PPC64, r13 is the thread pointer. Never allocate this register.
if (TM.isPPC64())
@@ -441,14 +442,11 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
bool PPCRegisterInfo::isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const {
- // We cannot use getReservedRegs() to find the registers that are not asm
- // clobberable because there are some reserved registers which can be
- // clobbered by inline asm. For example, when LR is clobbered, the register is
- // saved and restored. We will hardcode the registers that are not asm
- // cloberable in this function.
-
- // The stack pointer (R1/X1) is not clobberable by inline asm
- return PhysReg != PPC::R1 && PhysReg != PPC::X1;
+ // The counter registers are always reserved, but they are asm clobberable.
+ if (PhysReg == PPC::CTR || PhysReg == PPC::CTR8)
+ return true;
+
+ return !getReservedRegs(MF).test(PhysReg);
}
bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
index ccc36530c7957..03478150ed315 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi-mir.ll
@@ -1146,11 +1146,11 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 64BIT-NEXT: renamable $r11 = LWZ 0, %fixed-stack.1, implicit-def $x11 :: (load (s32) from %fixed-stack.1)
; 64BIT-NEXT: renamable $x12 = LWZ8 0, %fixed-stack.4 :: (load (s32) from %fixed-stack.4)
; 64BIT-NEXT: renamable $x0 = LWA 0, %fixed-stack.0 :: (load (s32) from %fixed-stack.0)
- ; 64BIT-NEXT: renamable $x31 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
- ; 64BIT-NEXT: renamable $x30 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
- ; 64BIT-NEXT: renamable $r29 = LWZ 0, %fixed-stack.5, implicit-def $x29 :: (load (s32) from %fixed-stack.5)
- ; 64BIT-NEXT: renamable $x28 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6)
- ; 64BIT-NEXT: renamable $x27 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16)
+ ; 64BIT-NEXT: renamable $x2 = LD 0, %fixed-stack.2 :: (load (s64) from %fixed-stack.2)
+ ; 64BIT-NEXT: renamable $x31 = LWA 0, %fixed-stack.3 :: (load (s32) from %fixed-stack.3)
+ ; 64BIT-NEXT: renamable $r30 = LWZ 0, %fixed-stack.5, implicit-def $x30 :: (load (s32) from %fixed-stack.5)
+ ; 64BIT-NEXT: renamable $x29 = LWA 0, %fixed-stack.6 :: (load (s32) from %fixed-stack.6)
+ ; 64BIT-NEXT: renamable $x28 = LD 0, %fixed-stack.7 :: (load (s64) from %fixed-stack.7, align 16)
; 64BIT-NEXT: renamable $r3 = nsw ADD4 renamable $r3, renamable $r4, implicit killed $x4, implicit killed $x3
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r5, implicit killed $x5
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r6, implicit killed $x6
@@ -1159,12 +1159,12 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r9, implicit killed $x9
; 64BIT-NEXT: renamable $r3 = nsw ADD4 killed renamable $r3, renamable $r10, implicit killed $x10
; 64BIT-NEXT: renamable $x3 = EXTSW_32_64 killed renamable $r3
- ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x27
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x28
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x29
- ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x30
+ ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x12
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x31
+ ; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x2
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x11
; 64BIT-NEXT: renamable $x3 = nsw ADD8 killed renamable $x3, killed renamable $x0
; 64BIT-NEXT: BLR8 implicit $lr8, implicit $rm, implicit $x3
diff --git a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
index 78d60f06c0678..433d427344466 100644
--- a/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
+++ b/llvm/test/CodeGen/PowerPC/aix-cc-abi.ll
@@ -1240,11 +1240,11 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; ASM64PWR4-NEXT: lwz 5, 132(1)
; ASM64PWR4-NEXT: add 3, 3, 4
; ASM64PWR4-NEXT: add 3, 3, 12
-; ASM64PWR4-NEXT: std 31, -8(1) # 8-byte Folded Spill
+; ASM64PWR4-NEXT: std 2, -8(1) # 8-byte Folded Spill
; ASM64PWR4-NEXT: add 3, 3, 5
-; ASM64PWR4-NEXT: lwz 31, 140(1)
+; ASM64PWR4-NEXT: lwz 2, 140(1)
; ASM64PWR4-NEXT: lwa 11, 148(1)
-; ASM64PWR4-NEXT: add 3, 3, 31
+; ASM64PWR4-NEXT: add 3, 3, 2
; ASM64PWR4-NEXT: add 3, 3, 11
; ASM64PWR4-NEXT: ld 4, 152(1)
; ASM64PWR4-NEXT: lwz 0, 164(1)
@@ -1252,7 +1252,7 @@ define i64 @test_ints_stack(i32 %i1, i32 %i2, i32 %i3, i32 %i4, i32 %i5, i32 %i6
; ASM64PWR4-NEXT: lwa 5, 172(1)
; ASM64PWR4-NEXT: add 3, 3, 0
; ASM64PWR4-NEXT: add 3, 3, 5
-; ASM64PWR4-NEXT: ld 31, -8(1) # 8-byte Folded Reload
+; ASM64PWR4-NEXT: ld 2, -8(1) # 8-byte Folded Reload
; ASM64PWR4-NEXT: blr
entry:
%add = add nsw i32 %i1, %i2
diff --git a/llvm/test/CodeGen/PowerPC/aix-inline-asm-clobber-warning.ll b/llvm/test/CodeGen/PowerPC/aix-inline-asm-clobber-warning.ll
new file mode 100644
index 0000000000000..0eb8cb207fd34
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/aix-inline-asm-clobber-warning.ll
@@ -0,0 +1,13 @@
+; RUN: llc < %s -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN: -mcpu=pwr7 -mattr=+altivec -O0 2>&1 | FileCheck %s
+
+; CHECK: warning: inline asm clobber list contains reserved registers: R2
+; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+
+ at a = external global i32, align 4
+
+define void @bar() {
+ store i32 0, ptr @a, align 4
+ call void asm sideeffect "li 2, 1", "~{r2}"()
+ ret void
+}
diff --git a/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir b/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
index 7d96f7feabe2b..407018c3e847e 100644
--- a/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
+++ b/llvm/test/CodeGen/PowerPC/aix64-csr-alloc.mir
@@ -17,6 +17,5 @@ body: |
BLR8 implicit $lr8, implicit undef $rm, implicit $x3, implicit $f1
...
# CHECK-DAG: AllocationOrder(VFRC) = [ $vf2 $vf3 $vf4 $vf5 $vf0 $vf1 $vf6 $vf7 $vf8 $vf9 $vf10 $vf11 $vf12 $vf13 $vf14 $vf15 $vf16 $vf17 $vf18 $vf19 $vf31 $vf30 $vf29 $vf28 $vf27 $vf26 $vf25 $vf24 $vf23 $vf22 $vf21 $vf20 ]
-# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x1
-# CHECK-DAG: 4 ]
-# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
\ No newline at end of file
+# CHECK-DAG: AllocationOrder(G8RC_and_G8RC_NOX0) = [ $x3 $x4 $x5 $x6 $x7 $x8 $x9 $x10 $x11 $x12 $x2 $x31 $x30 $x29 $x28 $x27 $x26 $x25 $x24 $x23 $x22 $x21 $x20 $x19 $x18 $x17 $x16 $x15 $x14 ]
+# CHECK-DAG: AllocationOrder(F8RC) = [ $f0 $f1 $f2 $f3 $f4 $f5 $f6 $f7 $f8 $f9 $f10 $f11 $f12 $f13 $f31 $f30 $f29 $f28 $f27 $f26 $f25 $f24 $f23 $f22 $f21 $f20 $f19 $f18 $f17 $f16 $f15 $f14 ]
diff --git a/llvm/test/CodeGen/PowerPC/inc-of-add.ll b/llvm/test/CodeGen/PowerPC/inc-of-add.ll
index c6d6f6a17b1b5..7bd748377f589 100644
--- a/llvm/test/CodeGen/PowerPC/inc-of-add.ll
+++ b/llvm/test/CodeGen/PowerPC/inc-of-add.ll
@@ -166,81 +166,81 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
;
; AIX-PPC64-LABEL: vector_i128_i8:
; AIX-PPC64: # %bb.0:
-; AIX-PPC64-NEXT: std 22, -80(1) # 8-byte Folded Spill
-; AIX-PPC64-NEXT: lbz 22, 207(1)
; AIX-PPC64-NEXT: std 23, -72(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT: lbz 23, 207(1)
; AIX-PPC64-NEXT: std 24, -64(1) # 8-byte Folded Spill
-; AIX-PPC64-NEXT: std 26, -48(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 25, -56(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT: std 27, -40(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT: std 26, -48(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT: std 30, -16(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 29, -24(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 28, -32(1) # 8-byte Folded Spill
-; AIX-PPC64-NEXT: std 27, -40(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT: std 2, -80(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 31, -8(1) # 8-byte Folded Spill
-; AIX-PPC64-NEXT: std 30, -16(1) # 8-byte Folded Spill
-; AIX-PPC64-NEXT: lbz 23, 199(1)
-; AIX-PPC64-NEXT: lbz 24, 191(1)
-; AIX-PPC64-NEXT: add 6, 22, 6
-; AIX-PPC64-NEXT: lbz 22, 231(1)
-; AIX-PPC64-NEXT: add 5, 23, 5
-; AIX-PPC64-NEXT: lbz 23, 223(1)
-; AIX-PPC64-NEXT: add 4, 24, 4
-; AIX-PPC64-NEXT: lbz 24, 215(1)
-; AIX-PPC64-NEXT: add 9, 22, 9
-; AIX-PPC64-NEXT: lbz 26, 127(1)
-; AIX-PPC64-NEXT: add 8, 23, 8
-; AIX-PPC64-NEXT: lbz 22, 255(1)
-; AIX-PPC64-NEXT: add 7, 24, 7
-; AIX-PPC64-NEXT: lbz 25, 119(1)
+; AIX-PPC64-NEXT: lbz 24, 199(1)
+; AIX-PPC64-NEXT: lbz 25, 191(1)
+; AIX-PPC64-NEXT: add 6, 23, 6
+; AIX-PPC64-NEXT: lbz 23, 231(1)
+; AIX-PPC64-NEXT: add 5, 24, 5
+; AIX-PPC64-NEXT: lbz 24, 223(1)
+; AIX-PPC64-NEXT: add 4, 25, 4
+; AIX-PPC64-NEXT: lbz 25, 215(1)
+; AIX-PPC64-NEXT: add 9, 23, 9
+; AIX-PPC64-NEXT: lbz 27, 127(1)
+; AIX-PPC64-NEXT: add 8, 24, 8
+; AIX-PPC64-NEXT: lbz 23, 255(1)
+; AIX-PPC64-NEXT: add 7, 25, 7
+; AIX-PPC64-NEXT: lbz 26, 119(1)
; AIX-PPC64-NEXT: addi 9, 9, 1
-; AIX-PPC64-NEXT: lbz 23, 247(1)
-; AIX-PPC64-NEXT: add 26, 22, 26
-; AIX-PPC64-NEXT: lbz 24, 239(1)
+; AIX-PPC64-NEXT: lbz 24, 247(1)
+; AIX-PPC64-NEXT: add 27, 23, 27
+; AIX-PPC64-NEXT: lbz 25, 239(1)
; AIX-PPC64-NEXT: addi 8, 8, 1
-; AIX-PPC64-NEXT: lbz 29, 151(1)
-; AIX-PPC64-NEXT: add 25, 23, 25
-; AIX-PPC64-NEXT: lbz 22, 279(1)
-; AIX-PPC64-NEXT: add 10, 24, 10
-; AIX-PPC64-NEXT: lbz 28, 143(1)
+; AIX-PPC64-NEXT: lbz 30, 151(1)
+; AIX-PPC64-NEXT: add 26, 24, 26
+; AIX-PPC64-NEXT: lbz 23, 279(1)
+; AIX-PPC64-NEXT: add 10, 25, 10
+; AIX-PPC64-NEXT: lbz 29, 143(1)
; AIX-PPC64-NEXT: addi 10, 10, 1
-; AIX-PPC64-NEXT: lbz 23, 271(1)
-; AIX-PPC64-NEXT: add 29, 22, 29
-; AIX-PPC64-NEXT: lbz 27, 135(1)
+; AIX-PPC64-NEXT: lbz 24, 271(1)
+; AIX-PPC64-NEXT: add 30, 23, 30
+; AIX-PPC64-NEXT: lbz 28, 135(1)
; AIX-PPC64-NEXT: addi 7, 7, 1
-; AIX-PPC64-NEXT: lbz 24, 263(1)
-; AIX-PPC64-NEXT: add 28, 23, 28
+; AIX-PPC64-NEXT: lbz 25, 263(1)
+; AIX-PPC64-NEXT: add 29, 24, 29
; AIX-PPC64-NEXT: lbz 11, 183(1)
; AIX-PPC64-NEXT: addi 6, 6, 1
-; AIX-PPC64-NEXT: lbz 22, 311(1)
-; AIX-PPC64-NEXT: add 27, 24, 27
+; AIX-PPC64-NEXT: lbz 23, 311(1)
+; AIX-PPC64-NEXT: add 28, 25, 28
; AIX-PPC64-NEXT: lbz 12, 175(1)
; AIX-PPC64-NEXT: addi 5, 5, 1
; AIX-PPC64-NEXT: lbz 0, 303(1)
-; AIX-PPC64-NEXT: add 11, 22, 11
-; AIX-PPC64-NEXT: lbz 31, 167(1)
+; AIX-PPC64-NEXT: add 11, 23, 11
+; AIX-PPC64-NEXT: lbz 2, 167(1)
; AIX-PPC64-NEXT: addi 11, 11, 1
-; AIX-PPC64-NEXT: lbz 23, 295(1)
+; AIX-PPC64-NEXT: lbz 24, 295(1)
; AIX-PPC64-NEXT: add 12, 0, 12
-; AIX-PPC64-NEXT: lbz 30, 159(1)
+; AIX-PPC64-NEXT: lbz 31, 159(1)
; AIX-PPC64-NEXT: addi 4, 4, 1
-; AIX-PPC64-NEXT: lbz 24, 287(1)
-; AIX-PPC64-NEXT: add 31, 23, 31
+; AIX-PPC64-NEXT: lbz 25, 287(1)
+; AIX-PPC64-NEXT: add 2, 24, 2
; AIX-PPC64-NEXT: stb 11, 15(3)
; AIX-PPC64-NEXT: addi 11, 12, 1
-; AIX-PPC64-NEXT: add 30, 24, 30
+; AIX-PPC64-NEXT: add 31, 25, 31
; AIX-PPC64-NEXT: stb 11, 14(3)
-; AIX-PPC64-NEXT: addi 11, 31, 1
+; AIX-PPC64-NEXT: addi 11, 2, 1
; AIX-PPC64-NEXT: stb 11, 13(3)
-; AIX-PPC64-NEXT: addi 11, 30, 1
+; AIX-PPC64-NEXT: addi 11, 31, 1
; AIX-PPC64-NEXT: stb 11, 12(3)
-; AIX-PPC64-NEXT: addi 11, 29, 1
+; AIX-PPC64-NEXT: addi 11, 30, 1
; AIX-PPC64-NEXT: stb 11, 11(3)
-; AIX-PPC64-NEXT: addi 11, 28, 1
+; AIX-PPC64-NEXT: addi 11, 29, 1
; AIX-PPC64-NEXT: stb 11, 10(3)
-; AIX-PPC64-NEXT: addi 11, 27, 1
+; AIX-PPC64-NEXT: addi 11, 28, 1
; AIX-PPC64-NEXT: stb 11, 9(3)
-; AIX-PPC64-NEXT: addi 11, 26, 1
+; AIX-PPC64-NEXT: addi 11, 27, 1
; AIX-PPC64-NEXT: stb 11, 8(3)
-; AIX-PPC64-NEXT: addi 11, 25, 1
+; AIX-PPC64-NEXT: addi 11, 26, 1
; AIX-PPC64-NEXT: stb 11, 7(3)
; AIX-PPC64-NEXT: stb 10, 6(3)
; AIX-PPC64-NEXT: stb 9, 5(3)
@@ -249,6 +249,7 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; AIX-PPC64-NEXT: stb 6, 2(3)
; AIX-PPC64-NEXT: stb 5, 1(3)
; AIX-PPC64-NEXT: stb 4, 0(3)
+; AIX-PPC64-NEXT: ld 2, -80(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 31, -8(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 29, -24(1) # 8-byte Folded Reload
@@ -258,7 +259,6 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; AIX-PPC64-NEXT: ld 25, -56(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 24, -64(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 23, -72(1) # 8-byte Folded Reload
-; AIX-PPC64-NEXT: ld 22, -80(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: blr
;
; PPC64LE-LABEL: vector_i128_i8:
@@ -314,30 +314,30 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
;
; AIX-PPC64-LABEL: vector_i128_i16:
; AIX-PPC64: # %bb.0:
-; AIX-PPC64-NEXT: std 26, -48(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 27, -40(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 28, -32(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 29, -24(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 30, -16(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: std 31, -8(1) # 8-byte Folded Spill
+; AIX-PPC64-NEXT: std 2, -48(1) # 8-byte Folded Spill
; AIX-PPC64-NEXT: lhz 11, 118(1)
; AIX-PPC64-NEXT: lhz 12, 182(1)
; AIX-PPC64-NEXT: lhz 0, 174(1)
-; AIX-PPC64-NEXT: lhz 31, 166(1)
+; AIX-PPC64-NEXT: lhz 2, 166(1)
; AIX-PPC64-NEXT: add 11, 12, 11
-; AIX-PPC64-NEXT: lhz 30, 158(1)
+; AIX-PPC64-NEXT: lhz 31, 158(1)
; AIX-PPC64-NEXT: add 10, 0, 10
-; AIX-PPC64-NEXT: lhz 29, 142(1)
-; AIX-PPC64-NEXT: add 9, 31, 9
-; AIX-PPC64-NEXT: lhz 28, 126(1)
-; AIX-PPC64-NEXT: add 8, 30, 8
-; AIX-PPC64-NEXT: lhz 27, 134(1)
-; AIX-PPC64-NEXT: add 6, 29, 6
-; AIX-PPC64-NEXT: lhz 26, 150(1)
-; AIX-PPC64-NEXT: add 4, 28, 4
-; AIX-PPC64-NEXT: add 5, 27, 5
+; AIX-PPC64-NEXT: lhz 30, 142(1)
+; AIX-PPC64-NEXT: add 9, 2, 9
+; AIX-PPC64-NEXT: lhz 29, 126(1)
+; AIX-PPC64-NEXT: add 8, 31, 8
+; AIX-PPC64-NEXT: lhz 28, 134(1)
+; AIX-PPC64-NEXT: add 6, 30, 6
+; AIX-PPC64-NEXT: lhz 27, 150(1)
+; AIX-PPC64-NEXT: add 4, 29, 4
+; AIX-PPC64-NEXT: add 5, 28, 5
; AIX-PPC64-NEXT: addi 11, 11, 1
-; AIX-PPC64-NEXT: add 7, 26, 7
+; AIX-PPC64-NEXT: add 7, 27, 7
; AIX-PPC64-NEXT: addi 10, 10, 1
; AIX-PPC64-NEXT: addi 9, 9, 1
; AIX-PPC64-NEXT: addi 8, 8, 1
@@ -353,12 +353,12 @@ define <8 x i16> @vector_i128_i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; AIX-PPC64-NEXT: sth 6, 4(3)
; AIX-PPC64-NEXT: sth 5, 2(3)
; AIX-PPC64-NEXT: sth 4, 0(3)
+; AIX-PPC64-NEXT: ld 2, -48(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 31, -8(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 28, -32(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: ld 27, -40(1) # 8-byte Folded Reload
-; AIX-PPC64-NEXT: ld 26, -48(1) # 8-byte Folded Reload
; AIX-PPC64-NEXT: blr
;
; PPC64LE-LABEL: vector_i128_i16:
diff --git a/llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll b/llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
index 7f13f5072d97f..ec91566e63864 100644
--- a/llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
+++ b/llvm/test/CodeGen/PowerPC/inline-asm-clobber-warning.ll
@@ -1,7 +1,7 @@
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc-unknown-unkown \
-; RUN: -mcpu=pwr7 2>&1 | FileCheck %s
+; RUN: -mcpu=pwr7 -O0 2>&1 | FileCheck %s
; RUN: llc < %s -verify-machineinstrs -mtriple=powerpc64-unknown-unkown \
-; RUN: -mcpu=pwr7 2>&1 | FileCheck %s
+; RUN: -mcpu=pwr7 -O0 2>&1 | FileCheck %s
define void @test_r1_clobber() {
entry:
@@ -20,3 +20,24 @@ entry:
; CHECK: warning: inline asm clobber list contains reserved registers: X1
; CHECK-NEXT: note: Reserved registers on the clobber list may not be preserved across the asm statement, and clobbering them may lead to undefined behaviour.
+
+; CHECK: warning: inline asm clobber list contains ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/99766
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