[clang] [llvm] [WIP][RISCV] Support __builtin_cpu_init and __builtin_cpu_supports (PR #99700)

[Piyou Chen via llvm-commits]

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@@ -1020,3 +1020,64 @@ std::string RISCVISAInfo::getTargetFeatureForExtension(StringRef Ext) {
   return isExperimentalExtension(Name) ? "experimental-" + Name.str()
                                        : Name.str();
 }
+
+struct RISCVExtBit {
+  const StringRef ext;
+  uint64_t bitpos;
+};
+
+/// Maps extensions with assigned bit positions within group 0 of
+/// __riscv_features_bits to their respective bit position.  At the
+/// moment all extensions are within group 0.
+static RISCVExtBit RISCVGroup0BitPositions[] = {
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BeMg wrote:

One reason we choose the `tablegen` approach is trying to maintain the everything relate to extension (In this case is groupID/bitPos) inside `RISCVFeatures.td`. 

How about land https://github.com/llvm/llvm-project/pull/94440 now, and replace this struct with tablegen generated `.inc` file? Or maybe we could replace it after 19.x release?



https://github.com/llvm/llvm-project/pull/99700