[llvm] [MVT][TableGen] Extend Machine Value Type to `uint16_t` (PR #99657)

[Pengcheng Wang via llvm-commits]

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@@ -27,13 +27,13 @@ def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
 // CHECK-NEXT: OPC_CheckChild1Integer, 0,
 // CHECK-NEXT: OPC_EmitInteger32, 0|128,2/*256*/,
 // CHECK-NEXT: OPC_MorphNodeTo1None, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS),
-// CHECK-NEXT:     MVT::i32, 2/*#Ops*/, 1, 0,
+// CHECK-NEXT:     7, 2/*#Ops*/, 1, 0,
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wangpc-pp wrote:

Make sense to me.

https://github.com/llvm/llvm-project/pull/99657