[llvm] [LLVM][AMDGPU] Copy isConvergent from Pseudo to Real instructions (PR #99658)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 19 08:10:20 PDT 2024
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Acim Maravic (Acim-Maravic)
<details>
<summary>Changes</summary>
This patch copies the flag isConevergent from pseudo instructions to the corresponding real instructions, so that isConvergent flag is also defined for real instructions.
Flags are not required by the compiler, but for consistency it would be nice to have them.
---
Full diff: https://github.com/llvm/llvm-project/pull/99658.diff
9 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (+3)
- (modified) llvm/lib/Target/AMDGPU/DSInstructions.td (+1)
- (modified) llvm/lib/Target/AMDGPU/FLATInstructions.td (+2)
- (modified) llvm/lib/Target/AMDGPU/SMInstructions.td (+1)
- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+5)
- (modified) llvm/lib/Target/AMDGPU/VOP1Instructions.td (+1)
- (modified) llvm/lib/Target/AMDGPU/VOP2Instructions.td (+1)
- (modified) llvm/lib/Target/AMDGPU/VOPCInstructions.td (+1)
- (modified) llvm/lib/Target/AMDGPU/VOPInstructions.td (+4)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index a904c8483dbf5..c6668b24f4ef6 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -139,6 +139,7 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let IsAtomicNoRet = ps.IsAtomicNoRet;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
bits<12> offset;
bits<5> cpol;
@@ -355,6 +356,7 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let LGKM_CNT = ps.LGKM_CNT;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
bits<12> offset;
bits<5> cpol;
@@ -2435,6 +2437,7 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let MTBUF = ps.MTBUF;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
bits<24> offset;
bits<8> vaddr;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 219246b71fe80..51f8d226c2bc1 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -73,6 +73,7 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let IsAtomicNoRet = ps.IsAtomicNoRet;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
let Constraints = ps.Constraints;
let DisableEncoding = ps.DisableEncoding;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index 88c6039473338..351563657aeb5 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -104,6 +104,7 @@ class FLAT_Real <bits<7> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
let VALU = ps.VALU;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
// encoding fields
bits<8> vaddr;
@@ -169,6 +170,7 @@ class VFLAT_Real <bits<8> op, FLAT_Pseudo ps, string opName = ps.Mnemonic> :
let VALU = ps.VALU;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
bits<7> saddr;
bits<8> vdst;
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index df1722b1f7fb4..30104fb122dbf 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -73,6 +73,7 @@ class SM_Real <SM_Pseudo ps, string opName = ps.Mnemonic>
let IsAtomicNoRet = ps.IsAtomicNoRet;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
let TSFlags = ps.TSFlags;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index 0d6883254c350..de3191bd91df6 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -67,6 +67,7 @@ class SOP1_Real<bits<8> op, SOP1_Pseudo ps, string real_name = ps.Mnemonic> :
let isBarrier = ps.isBarrier;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
// encoding
bits<7> sdst;
@@ -579,6 +580,7 @@ class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :
let DisableEncoding = ps.DisableEncoding;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
// encoding
bits<7> sdst;
@@ -996,6 +998,7 @@ class SOPK_Real<SOPK_Pseudo ps, string name = ps.Mnemonic> :
let isBarrier = ps.isBarrier;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
// encoding
bits<7> sdst;
@@ -1262,6 +1265,7 @@ class SOPC_Real<bits<7> op, SOPC_Pseudo ps> :
let mayStore = ps.mayStore;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
// encoding
bits<8> src0;
@@ -1459,6 +1463,7 @@ class SOPP_Real<SOPP_Pseudo ps, string name = ps.Mnemonic> :
let isBarrier = ps.isBarrier;
let Uses = ps.Uses;
let Defs = ps.Defs;
+ let isConvergent = ps.isConvergent;
bits <16> simm16;
}
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 2c0d61ee4afa1..8bb1374a78c4d 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -88,6 +88,7 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let TRANS = ps.TRANS;
+ let isConvergent = ps.isConvergent;
}
class VOP1_Real_Gen <VOP1_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 9989752c2f6bc..44eb5f5abafe0 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -107,6 +107,7 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let isConvergent = ps.isConvergent;
}
class VOP2_Real_Gen <VOP2_Pseudo ps, GFXGen Gen, string real_name = ps.Mnemonic> :
diff --git a/llvm/lib/Target/AMDGPU/VOPCInstructions.td b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
index 3bcee28a2cb78..62ca6261c47c8 100644
--- a/llvm/lib/Target/AMDGPU/VOPCInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPCInstructions.td
@@ -180,6 +180,7 @@ class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily, string asm_name = ps.Pseudo
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
+ let isConvergent = ps.isConvergent;
}
class VOPC_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td
index f2ed17ac305a1..3851415ab0cae 100644
--- a/llvm/lib/Target/AMDGPU/VOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td
@@ -194,6 +194,7 @@ class VOP3_Real <VOP_Pseudo ps, int EncodingFamily, string asm_name = ps.Mnemoni
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let TRANS = ps.TRANS;
+ let isConvergent = ps.isConvergent;
VOPProfile Pfl = ps.Pfl;
}
@@ -653,6 +654,7 @@ class VOP_SDWA_Real <VOP_SDWA_Pseudo ps> :
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let TRANS = ps.TRANS;
+ let isConvergent = ps.isConvergent;
}
class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
@@ -689,6 +691,7 @@ class Base_VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let TRANS = ps.TRANS;
+ let isConvergent = ps.isConvergent;
}
class VOP_SDWA9_Real <VOP_SDWA_Pseudo ps> :
@@ -889,6 +892,7 @@ class VOP_DPP_Real <VOP_DPP_Pseudo ps, int EncodingFamily> :
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let TRANS = ps.TRANS;
+ let isConvergent = ps.isConvergent;
}
class VOP_DPP_Base <string OpName, VOPProfile P,
``````````
</details>
https://github.com/llvm/llvm-project/pull/99658
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