[llvm] 4c28494 - [SLP][NFC]Add a test for incorrect minbitwidth analysis for trunc'ed bv, NFC.

[Alexey Bataev via llvm-commits]

Author: Alexey Bataev
Date: 2024-07-19T07:14:03-07:00
New Revision: 4c28494e7842b26a566f9406f71510eda4a9e576

URL: https://github.com/llvm/llvm-project/commit/4c28494e7842b26a566f9406f71510eda4a9e576
DIFF: https://github.com/llvm/llvm-project/commit/4c28494e7842b26a566f9406f71510eda4a9e576.diff

LOG: [SLP][NFC]Add a test for incorrect minbitwidth analysis for trunc'ed bv, NFC.

Added: 
    llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll

Modified: 
    

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
new file mode 100644
index 0000000000000..53acc37155c9f
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/trunc-bv-multi-uses.ll
@@ -0,0 +1,31 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
+; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr="+v" < %s -slp-threshold=-10 | FileCheck %s
+
+define i32 @test(i64 %v1, i64 %v2) {
+; CHECK-LABEL: define i32 @test(
+; CHECK-SAME: i64 [[V1:%.*]], i64 [[V2:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <2 x i64> poison, i64 [[V1]], i32 0
+; CHECK-NEXT:    [[TMP1:%.*]] = insertelement <2 x i64> [[TMP0]], i64 [[V2]], i32 1
+; CHECK-NEXT:    [[TMP2:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>
+; CHECK-NEXT:    [[TMP3:%.*]] = sext <2 x i32> [[TMP2]] to <2 x i64>
+; CHECK-NEXT:    [[TMP4:%.*]] = lshr <2 x i64> [[TMP3]], <i64 32, i64 32>
+; CHECK-NEXT:    [[TMP5:%.*]] = trunc <2 x i64> [[TMP4]] to <2 x i32>
+; CHECK-NEXT:    [[TMP6:%.*]] = add <2 x i32> [[TMP2]], [[TMP5]]
+; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <2 x i32> [[TMP6]], i32 0
+; CHECK-NEXT:    [[TMP8:%.*]] = extractelement <2 x i32> [[TMP6]], i32 1
+; CHECK-NEXT:    [[MUL:%.*]] = mul i32 [[TMP7]], [[TMP8]]
+; CHECK-NEXT:    ret i32 [[MUL]]
+;
+entry:
+  %t1 = trunc i64 %v1 to i32
+  %t2 = trunc i64 %v2 to i32
+  %lshr1 = lshr i64 %v1, 32
+  %lshr2 = lshr i64 %v2, 32
+  %t3 = trunc i64 %lshr1 to i32
+  %t4 = trunc i64 %lshr2 to i32
+  %add1 = add i32 %t1, %t3
+  %add2 = add i32 %t2, %t4
+  %mul = mul i32 %add1, %add2
+  ret i32 %mul
+}