[llvm] [RISCV] Implement trampolines for rv64 (PR #96309)
Roger Ferrer Ibáñez via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 19 06:55:35 PDT 2024
https://github.com/rofirrim updated https://github.com/llvm/llvm-project/pull/96309
>From cbc0aa2d3e14fa2952b55574d05308e1e4555049 Mon Sep 17 00:00:00 2001
From: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
Date: Thu, 20 Jun 2024 06:49:11 +0000
Subject: [PATCH 1/4] [RISCV] Implement trampolines for rv64
This is implementation is heavily based on what the X86 target does but
emitting the instructions that GCC emits for rv64.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 126 ++++++++++++++++++++
llvm/lib/Target/RISCV/RISCVISelLowering.h | 3 +
llvm/test/CodeGen/RISCV/rv64-trampoline.ll | 80 +++++++++++++
3 files changed, 209 insertions(+)
create mode 100644 llvm/test/CodeGen/RISCV/rv64-trampoline.ll
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index e938454b8e642..b2be3811c9e7d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -633,6 +633,11 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::READSTEADYCOUNTER, MVT::i64,
Subtarget.is64Bit() ? Legal : Custom);
+ if (Subtarget.is64Bit()) {
+ setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
+ setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
+ }
+
setOperationAction({ISD::TRAP, ISD::DEBUGTRAP}, MVT::Other, Legal);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
if (Subtarget.is64Bit())
@@ -7263,6 +7268,10 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
return emitFlushICache(DAG, Op.getOperand(0), Op.getOperand(1),
Op.getOperand(2), Flags, DL);
}
+ case ISD::INIT_TRAMPOLINE:
+ return lowerINIT_TRAMPOLINE(Op, DAG);
+ case ISD::ADJUST_TRAMPOLINE:
+ return lowerADJUST_TRAMPOLINE(Op, DAG);
}
}
@@ -7278,6 +7287,123 @@ SDValue RISCVTargetLowering::emitFlushICache(SelectionDAG &DAG, SDValue InChain,
return CallResult.second;
}
+SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
+ SelectionDAG &DAG) const {
+ if (!Subtarget.is64Bit())
+ llvm::report_fatal_error("Trampolines only implemented for RV64");
+
+ SDValue Root = Op.getOperand(0);
+ SDValue Trmp = Op.getOperand(1); // trampoline
+ SDLoc dl(Op);
+
+ const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
+
+ // We store in the trampoline buffer the following instructions and data.
+ // Offset:
+ // 0: auipc t2, 0
+ // 4: ld t0, 24(t2)
+ // 8: ld t2, 16(t2)
+ // 12: jalr t0
+ // 16: <StaticChainOffset>
+ // 24: <FunctionAddressOffset>
+ // 32:
+
+ // Constants shamelessly taken from GCC.
+ constexpr unsigned Opcode_AUIPC = 0x17;
+ constexpr unsigned Opcode_LD = 0x3003;
+ constexpr unsigned Opcode_JALR = 0x67;
+ constexpr unsigned ShiftField_RD = 7;
+ constexpr unsigned ShiftField_RS1 = 15;
+ constexpr unsigned ShiftField_IMM = 20;
+ constexpr unsigned Reg_X5 = 0x5; // x5/t0 (holds the address to the function)
+ constexpr unsigned Reg_X7 = 0x7; // x7/t2 (holds the static chain)
+
+ constexpr unsigned StaticChainOffset = 16;
+ constexpr unsigned FunctionAddressOffset = 24;
+
+ SDValue OutChains[6];
+ SDValue Addr = Trmp;
+
+ // auipc t2, 0
+ // Loads the current PC into t2.
+ constexpr uint32_t AUIPC_X7_0 =
+ Opcode_AUIPC | (Reg_X7 << ShiftField_RD);
+ OutChains[0] =
+ DAG.getTruncStore(Root, dl, DAG.getConstant(AUIPC_X7_0, dl, MVT::i64),
+ Addr, MachinePointerInfo(TrmpAddr), MVT::i32);
+
+ // ld t0, 24(t2)
+ // Loads the function address into t0. Note that we are using offsets
+ // pc-relative to the first instruction of the trampoline.
+ const uint32_t LD_X5_TargetFunctionOffset =
+ Opcode_LD | (Reg_X5 << ShiftField_RD) |
+ (Reg_X7 << ShiftField_RS1) | (FunctionAddressOffset << ShiftField_IMM);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(4, dl, MVT::i64));
+ OutChains[1] = DAG.getTruncStore(
+ Root, dl,
+ DAG.getConstant(LD_X5_TargetFunctionOffset, dl, MVT::i64), Addr,
+ MachinePointerInfo(TrmpAddr, 4), MVT::i32);
+
+ // ld t2, 16(t2)
+ // Load the value of the static chain.
+ const uint32_t LD_X7_StaticChainOffset =
+ Opcode_LD | (Reg_X7 << ShiftField_RD) |
+ (Reg_X7 << ShiftField_RS1) | (StaticChainOffset << ShiftField_IMM);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(8, dl, MVT::i64));
+ OutChains[2] = DAG.getTruncStore(
+ Root, dl, DAG.getConstant(LD_X7_StaticChainOffset, dl, MVT::i64),
+ Addr, MachinePointerInfo(TrmpAddr, 8), MVT::i32);
+
+ // jalr t0
+ // Jump to the function.
+ const uint32_t JALR_X5 =
+ Opcode_JALR | (Reg_X5 << ShiftField_RS1);
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(12, dl, MVT::i64));
+ OutChains[3] =
+ DAG.getTruncStore(Root, dl, DAG.getConstant(JALR_X5, dl, MVT::i64), Addr,
+ MachinePointerInfo(TrmpAddr, 12), MVT::i32);
+
+ // Now store the variable part of the trampoline.
+ SDValue FunctionAddress = Op.getOperand(2);
+ SDValue StaticChain = Op.getOperand(3);
+
+ // Store the given static chain in the trampoline buffer.
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(StaticChainOffset, dl, MVT::i64));
+ OutChains[4] = DAG.getStore(Root, dl, StaticChain, Addr,
+ MachinePointerInfo(TrmpAddr, StaticChainOffset));
+
+ // Store the given function address in the trampoline buffer.
+ Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(FunctionAddressOffset, dl, MVT::i64));
+ OutChains[5] =
+ DAG.getStore(Root, dl, FunctionAddress, Addr,
+ MachinePointerInfo(TrmpAddr, FunctionAddressOffset));
+
+ SDValue StoreToken = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
+
+ // Compute end of trampoline.
+ SDValue EndOfTrmp = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
+ DAG.getConstant(32, dl, MVT::i64));
+
+ // Call clear cache on the trampoline buffer.
+ SDValue Chain = DAG.getNode(ISD::CLEAR_CACHE, dl, MVT::Other, StoreToken,
+ Trmp, EndOfTrmp);
+
+ return Chain;
+}
+
+SDValue RISCVTargetLowering::lowerADJUST_TRAMPOLINE(SDValue Op,
+ SelectionDAG &DAG) const {
+ if (!Subtarget.is64Bit())
+ llvm::report_fatal_error("Trampolines only implemented for RV64");
+
+ return Op.getOperand(0);
+}
+
static SDValue getTargetNode(GlobalAddressSDNode *N, const SDLoc &DL, EVT Ty,
SelectionDAG &DAG, unsigned Flags) {
return DAG.getTargetGlobalAddress(N->getGlobal(), DL, Ty, 0, Flags);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 0b0ad9229f0b3..79c7e13935d4c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -995,6 +995,9 @@ class RISCVTargetLowering : public TargetLowering {
SDValue expandUnalignedRVVLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue expandUnalignedRVVStore(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
+
bool isEligibleForTailCallOptimization(
CCState &CCInfo, CallLoweringInfo &CLI, MachineFunction &MF,
const SmallVector<CCValAssign, 16> &ArgLocs) const;
diff --git a/llvm/test/CodeGen/RISCV/rv64-trampoline.ll b/llvm/test/CodeGen/RISCV/rv64-trampoline.ll
new file mode 100644
index 0000000000000..4a7a50fc09bf8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/rv64-trampoline.ll
@@ -0,0 +1,80 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64 %s
+; RUN: llc -mtriple=riscv64-unknown-linux-gnu -verify-machineinstrs < %s \
+; RUN: | FileCheck -check-prefix=RV64-LINUX %s
+
+declare void @llvm.init.trampoline(ptr, ptr, ptr)
+declare ptr @llvm.adjust.trampoline(ptr)
+declare i64 @f(ptr nest, i64)
+
+define i64 @test0(i64 %n, ptr %p) nounwind {
+; RV64-LABEL: test0:
+; RV64: # %bb.0:
+; RV64-NEXT: addi sp, sp, -64
+; RV64-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-NEXT: mv s0, a0
+; RV64-NEXT: lui a0, %hi(.LCPI0_0)
+; RV64-NEXT: ld a0, %lo(.LCPI0_0)(a0)
+; RV64-NEXT: lui a2, %hi(f)
+; RV64-NEXT: addi a2, a2, %lo(f)
+; RV64-NEXT: sd a2, 32(sp)
+; RV64-NEXT: sd a1, 24(sp)
+; RV64-NEXT: sd a0, 16(sp)
+; RV64-NEXT: lui a0, 6203
+; RV64-NEXT: addi a0, a0, 643
+; RV64-NEXT: slli a0, a0, 32
+; RV64-NEXT: addi a0, a0, 919
+; RV64-NEXT: sd a0, 8(sp)
+; RV64-NEXT: addi a1, sp, 40
+; RV64-NEXT: addi a0, sp, 8
+; RV64-NEXT: addi s1, sp, 8
+; RV64-NEXT: call __clear_cache
+; RV64-NEXT: mv a0, s0
+; RV64-NEXT: jalr s1
+; RV64-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-NEXT: addi sp, sp, 64
+; RV64-NEXT: ret
+;
+; RV64-LINUX-LABEL: test0:
+; RV64-LINUX: # %bb.0:
+; RV64-LINUX-NEXT: addi sp, sp, -64
+; RV64-LINUX-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
+; RV64-LINUX-NEXT: sd s0, 48(sp) # 8-byte Folded Spill
+; RV64-LINUX-NEXT: sd s1, 40(sp) # 8-byte Folded Spill
+; RV64-LINUX-NEXT: mv s0, a0
+; RV64-LINUX-NEXT: lui a0, %hi(.LCPI0_0)
+; RV64-LINUX-NEXT: ld a0, %lo(.LCPI0_0)(a0)
+; RV64-LINUX-NEXT: lui a2, %hi(f)
+; RV64-LINUX-NEXT: addi a2, a2, %lo(f)
+; RV64-LINUX-NEXT: sd a2, 32(sp)
+; RV64-LINUX-NEXT: sd a1, 24(sp)
+; RV64-LINUX-NEXT: sd a0, 16(sp)
+; RV64-LINUX-NEXT: lui a0, 6203
+; RV64-LINUX-NEXT: addi a0, a0, 643
+; RV64-LINUX-NEXT: slli a0, a0, 32
+; RV64-LINUX-NEXT: addi a0, a0, 919
+; RV64-LINUX-NEXT: sd a0, 8(sp)
+; RV64-LINUX-NEXT: addi a1, sp, 40
+; RV64-LINUX-NEXT: addi a0, sp, 8
+; RV64-LINUX-NEXT: addi s1, sp, 8
+; RV64-LINUX-NEXT: li a2, 0
+; RV64-LINUX-NEXT: call __riscv_flush_icache
+; RV64-LINUX-NEXT: mv a0, s0
+; RV64-LINUX-NEXT: jalr s1
+; RV64-LINUX-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
+; RV64-LINUX-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
+; RV64-LINUX-NEXT: ld s1, 40(sp) # 8-byte Folded Reload
+; RV64-LINUX-NEXT: addi sp, sp, 64
+; RV64-LINUX-NEXT: ret
+ %alloca = alloca [32 x i8], align 8
+ call void @llvm.init.trampoline(ptr %alloca, ptr @f, ptr %p)
+ %tramp = call ptr @llvm.adjust.trampoline(ptr %alloca)
+ %ret = call i64 %tramp(i64 %n)
+ ret i64 %ret
+
+}
>From ebaf74f98b59a1be4800d1b7d5569e78308264ac Mon Sep 17 00:00:00 2001
From: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
Date: Fri, 19 Jul 2024 07:27:15 +0000
Subject: [PATCH 2/4] Use MCCodeEmitter to encode instructions rather than
hardcoded constants
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 56 +++++++++++++--------
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index b2be3811c9e7d..afb69c8aefb76 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -37,6 +37,8 @@
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsRISCV.h"
#include "llvm/IR/PatternMatch.h"
+#include "llvm/MC/MCCodeEmitter.h"
+#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
@@ -7292,6 +7294,14 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
if (!Subtarget.is64Bit())
llvm::report_fatal_error("Trampolines only implemented for RV64");
+ // Create an MCCodeEmitter to encode instructions.
+ TargetLoweringObjectFile *TLO = getTargetMachine().getObjFileLowering();
+ assert(TLO);
+ MCContext& MCCtx = TLO->getContext();
+
+ std::unique_ptr<MCCodeEmitter> CodeEmitter(
+ createRISCVMCCodeEmitter(*getTargetMachine().getMCInstrInfo(), MCCtx));
+
SDValue Root = Op.getOperand(0);
SDValue Trmp = Op.getOperand(1); // trampoline
SDLoc dl(Op);
@@ -7308,26 +7318,30 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// 24: <FunctionAddressOffset>
// 32:
- // Constants shamelessly taken from GCC.
- constexpr unsigned Opcode_AUIPC = 0x17;
- constexpr unsigned Opcode_LD = 0x3003;
- constexpr unsigned Opcode_JALR = 0x67;
- constexpr unsigned ShiftField_RD = 7;
- constexpr unsigned ShiftField_RS1 = 15;
- constexpr unsigned ShiftField_IMM = 20;
- constexpr unsigned Reg_X5 = 0x5; // x5/t0 (holds the address to the function)
- constexpr unsigned Reg_X7 = 0x7; // x7/t2 (holds the static chain)
-
constexpr unsigned StaticChainOffset = 16;
constexpr unsigned FunctionAddressOffset = 24;
+ auto GetEncoding = [&](const MCInst &MC) {
+ SmallVector<char, 4> CB;
+ SmallVector<MCFixup> Fixups;
+ const MCSubtargetInfo *STI = getTargetMachine().getMCSubtargetInfo();
+ assert(STI);
+ CodeEmitter->encodeInstruction(MC, CB, Fixups, *STI);
+ assert(CB.size() == 4);
+ assert(Fixups.empty());
+ uint32_t Encoding = support::endian::read32le(CB.data());
+ return Encoding;
+ };
+
SDValue OutChains[6];
SDValue Addr = Trmp;
// auipc t2, 0
// Loads the current PC into t2.
- constexpr uint32_t AUIPC_X7_0 =
- Opcode_AUIPC | (Reg_X7 << ShiftField_RD);
+ MCInst AUIPC_X7_0_Inst =
+ MCInstBuilder(RISCV::AUIPC).addReg(RISCV::X7).addImm(0);
+
+ uint32_t AUIPC_X7_0 = GetEncoding(AUIPC_X7_0_Inst);
OutChains[0] =
DAG.getTruncStore(Root, dl, DAG.getConstant(AUIPC_X7_0, dl, MVT::i64),
Addr, MachinePointerInfo(TrmpAddr), MVT::i32);
@@ -7335,9 +7349,10 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// ld t0, 24(t2)
// Loads the function address into t0. Note that we are using offsets
// pc-relative to the first instruction of the trampoline.
- const uint32_t LD_X5_TargetFunctionOffset =
- Opcode_LD | (Reg_X5 << ShiftField_RD) |
- (Reg_X7 << ShiftField_RS1) | (FunctionAddressOffset << ShiftField_IMM);
+ MCInst LD_X5_TargetFunctionOffset_Inst =
+ MCInstBuilder(RISCV::LD).addReg(RISCV::X5).addReg(RISCV::X7).addImm(24);
+ uint32_t LD_X5_TargetFunctionOffset =
+ GetEncoding(LD_X5_TargetFunctionOffset_Inst);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(4, dl, MVT::i64));
OutChains[1] = DAG.getTruncStore(
@@ -7347,9 +7362,9 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// ld t2, 16(t2)
// Load the value of the static chain.
- const uint32_t LD_X7_StaticChainOffset =
- Opcode_LD | (Reg_X7 << ShiftField_RD) |
- (Reg_X7 << ShiftField_RS1) | (StaticChainOffset << ShiftField_IMM);
+ MCInst LD_X7_StaticChainOffset_Inst =
+ MCInstBuilder(RISCV::LD).addReg(RISCV::X7).addReg(RISCV::X7).addImm(16);
+ uint32_t LD_X7_StaticChainOffset = GetEncoding(LD_X7_StaticChainOffset_Inst);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(8, dl, MVT::i64));
OutChains[2] = DAG.getTruncStore(
@@ -7358,8 +7373,9 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// jalr t0
// Jump to the function.
- const uint32_t JALR_X5 =
- Opcode_JALR | (Reg_X5 << ShiftField_RS1);
+ MCInst JALR_X5_Inst =
+ MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(RISCV::X5).addImm(0);
+ uint32_t JALR_X5 = GetEncoding(JALR_X5_Inst);
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(12, dl, MVT::i64));
OutChains[3] =
>From 1f101f6d6a170c6a4591bb4d6b32ec537b060b77 Mon Sep 17 00:00:00 2001
From: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
Date: Fri, 19 Jul 2024 07:51:44 +0000
Subject: [PATCH 3/4] Remove stray blank line
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index afb69c8aefb76..0ebd799b4935c 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7340,7 +7340,6 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// Loads the current PC into t2.
MCInst AUIPC_X7_0_Inst =
MCInstBuilder(RISCV::AUIPC).addReg(RISCV::X7).addImm(0);
-
uint32_t AUIPC_X7_0 = GetEncoding(AUIPC_X7_0_Inst);
OutChains[0] =
DAG.getTruncStore(Root, dl, DAG.getConstant(AUIPC_X7_0, dl, MVT::i64),
>From 7941782fe0c86040199783172fb4563d42e0f6bc Mon Sep 17 00:00:00 2001
From: Roger Ferrer Ibanez <roger.ferrer at bsc.es>
Date: Fri, 19 Jul 2024 13:50:52 +0000
Subject: [PATCH 4/4] clang-format
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 0ebd799b4935c..bc7584e12296d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7297,7 +7297,7 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
// Create an MCCodeEmitter to encode instructions.
TargetLoweringObjectFile *TLO = getTargetMachine().getObjFileLowering();
assert(TLO);
- MCContext& MCCtx = TLO->getContext();
+ MCContext &MCCtx = TLO->getContext();
std::unique_ptr<MCCodeEmitter> CodeEmitter(
createRISCVMCCodeEmitter(*getTargetMachine().getMCInstrInfo(), MCCtx));
@@ -7355,8 +7355,7 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(4, dl, MVT::i64));
OutChains[1] = DAG.getTruncStore(
- Root, dl,
- DAG.getConstant(LD_X5_TargetFunctionOffset, dl, MVT::i64), Addr,
+ Root, dl, DAG.getConstant(LD_X5_TargetFunctionOffset, dl, MVT::i64), Addr,
MachinePointerInfo(TrmpAddr, 4), MVT::i32);
// ld t2, 16(t2)
@@ -7367,8 +7366,8 @@ SDValue RISCVTargetLowering::lowerINIT_TRAMPOLINE(SDValue Op,
Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp,
DAG.getConstant(8, dl, MVT::i64));
OutChains[2] = DAG.getTruncStore(
- Root, dl, DAG.getConstant(LD_X7_StaticChainOffset, dl, MVT::i64),
- Addr, MachinePointerInfo(TrmpAddr, 8), MVT::i32);
+ Root, dl, DAG.getConstant(LD_X7_StaticChainOffset, dl, MVT::i64), Addr,
+ MachinePointerInfo(TrmpAddr, 8), MVT::i32);
// jalr t0
// Jump to the function.
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