[llvm] [AMDGPU] Inplace FI elimination during PEI for scalar copy instruction (PR #99556)

via llvm-commits llvm-commits at lists.llvm.org
Fri Jul 19 06:34:57 PDT 2024


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``````````bash
git-clang-format --diff 5e8cd29d62a72ed18e7bc782554d7f14eccec0ee 126bd3078ec68c9b1abcc99d0bb61048d89c9011 --extensions cpp -- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 2f210f4dde..c94595f3dd 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -2532,11 +2532,11 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
 
             // We may have 1 free scratch SGPR even though a carry out is
             // unavailable. Only one additional mov is needed.
-            Register TmpScaledReg =
-                IsCopy && IsSALU
-                    ? ResultReg
-                    : RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
-                                                    MI, false, 0, /*AllowSpill=*/false);
+            Register TmpScaledReg = IsCopy && IsSALU
+                                        ? ResultReg
+                                        : RS->scavengeRegisterBackwards(
+                                              AMDGPU::SReg_32_XM0RegClass, MI,
+                                              false, 0, /*AllowSpill=*/false);
             Register ScaledReg =
                 TmpScaledReg.isValid() ? TmpScaledReg : FrameReg;
             Register TmpResultReg = ScaledReg;
@@ -2558,10 +2558,10 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
               auto Add = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ADD_U32_e32),
                                  TmpResultReg);
               Add.addImm(Offset).addReg(TmpResultReg, RegState::Kill);
-              Register NewDest =
-                  IsCopy ? ResultReg
-                         : RS->scavengeRegisterBackwards(
-                               AMDGPU::SReg_32RegClass, Add, false, 0, /*AllowSpill=*/true);
+              Register NewDest = IsCopy ? ResultReg
+                                        : RS->scavengeRegisterBackwards(
+                                              AMDGPU::SReg_32RegClass, Add,
+                                              false, 0, /*AllowSpill=*/true);
               BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
                       NewDest)
                   .addReg(TmpResultReg);

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https://github.com/llvm/llvm-project/pull/99556


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