[llvm] [Tablegen] Support Operand in morphing patterns (PR #99645)

[Serge Pavlov via llvm-commits]

https://github.com/spavloff created https://github.com/llvm/llvm-project/pull/99645

Previously TableGen crashed on a pattern that has custom operand in the source part. Such patterns appear in RISCV selector, static rounding mode is represented by custom operand.

>From 31a210ec14523518585c122c1b526e790a588f53 Mon Sep 17 00:00:00 2001
From: Serge Pavlov <sepavloff at gmail.com>
Date: Fri, 19 Jul 2024 18:00:33 +0700
Subject: [PATCH] [Tablegen] Support Operand in morphing patterns

Previously TableGen crashed on a pattern that has custom operand in the
source part. Such patterns appear in RISCV selector, static rounding
mode is represented by custom operand.
---
 llvm/test/TableGen/pattern-operand.td     | 34 +++++++++++++++++++++++
 llvm/utils/TableGen/DAGISelMatcherGen.cpp |  6 ++++
 2 files changed, 40 insertions(+)
 create mode 100644 llvm/test/TableGen/pattern-operand.td

diff --git a/llvm/test/TableGen/pattern-operand.td b/llvm/test/TableGen/pattern-operand.td
new file mode 100644
index 0000000000000..0bda0c26a937a
--- /dev/null
+++ b/llvm/test/TableGen/pattern-operand.td
@@ -0,0 +1,34 @@
+// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTargetInstrInfo : InstrInfo;
+
+def TestTarget : Target {
+  let InstructionSet = TestTargetInstrInfo;
+}
+
+def REG : Register<"REG">;
+def GPR : RegisterClass<"TestTarget", [i32], 32, (add REG)>;
+
+def frmarg : Operand<i8> {}
+
+def INSTR : Instruction {
+  let OutOperandList = (outs GPR:$rd);
+  let InOperandList = (ins GPR:$rs1, frmarg:$rm);
+  let Pattern = [];
+}
+
+def SDTTest : SDTypeProfile<1, 2, [SDTCisSameAs<0, 1>]>;
+def test_node : SDNode<"ISD::INSTR", SDTTest>;
+
+def : Pat<(test_node (i32 GPR:$rs1), frmarg:$rm),
+          (INSTR $rs1, $rm)>;
+
+// CHECK: MatcherTable[] = {
+// CHECK:   OPC_CheckOpcode, TARGET_VAL(ISD::INSTR),
+// CHECK:   OPC_RecordChild0,
+// CHECK:   OPC_RecordChild1,
+// CHECK:   OPC_CheckTypeI32,
+// CHECK:   OPC_MorphNodeTo1None, TARGET_VAL(::INSTR),
+// CHECK:       MVT::i32, 2/*#Ops*/, 0, 1, 
diff --git a/llvm/utils/TableGen/DAGISelMatcherGen.cpp b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
index db3fe8d2993f2..1c69e2e45cdd7 100644
--- a/llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ b/llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -294,6 +294,12 @@ void MatcherGen::EmitLeafMatchCode(const TreePatternNode &N) {
     return;
   }
 
+  if (LeafRec->isSubClassOf("Operand")) {
+    assert(LeafRec->getValueAsDef("Type")->isSubClassOf("ValueType"));
+    // Operand matches as its ValueType.
+    return;
+  }
+
   errs() << "Unknown leaf kind: " << N << "\n";
   abort();
 }