[llvm] [AArch64] Lower scalable i1 vector add reduction to cntp (PR #99031)

[via llvm-commits]

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git-clang-format --diff 31015240d366e4bf6f114856caa6e9ce90742b7f 09025adec525441898484a0828be3674bc26c760 --extensions cpp -- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e8bf2f8c21..afb208e78a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -27477,8 +27477,8 @@ SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,
       // CNTP(BoolVec & BoolVec) <=> CNTP(BoolVec & PTRUE)
       SDValue CntpOp = DAG.getNode(
           ISD::INTRINSIC_WO_CHAIN, DL, MVT::i64,
-          DAG.getTargetConstant(Intrinsic::aarch64_sve_cntp, DL, MVT::i64), BoolVec,
-          BoolVec);
+          DAG.getTargetConstant(Intrinsic::aarch64_sve_cntp, DL, MVT::i64),
+          BoolVec, BoolVec);
       return DAG.getAnyExtOrTrunc(CntpOp, DL, ScalarOp.getValueType());
     }
   }

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https://github.com/llvm/llvm-project/pull/99031