[llvm] [GlobalIsel] import G_SCMP and G_UCMP (PR #99518)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-aarch64

Author: Thorsten Schütt (tschuett)

<details>
<summary>Changes</summary>

See https://github.com/llvm/llvm-project/pull/98894

---
Full diff: https://github.com/llvm/llvm-project/pull/99518.diff


2 Files Affected:

- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+12) 
- (added) llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll (+54) 


``````````diff
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 72dff12423ced..a6b454d41a76f 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2561,6 +2561,18 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
     MIRBuilder.buildVScale(getOrCreateVReg(CI), 1);
     return true;
   }
+  case Intrinsic::scmp: {
+    MIRBuilder.buildSCmp(getOrCreateVReg(CI),
+                         getOrCreateVReg(*CI.getOperand(0)),
+                         getOrCreateVReg(*CI.getOperand(1)));
+    return true;
+  }
+  case Intrinsic::ucmp: {
+    MIRBuilder.buildUCmp(getOrCreateVReg(CI),
+                         getOrCreateVReg(*CI.getOperand(0)),
+                         getOrCreateVReg(*CI.getOperand(1)));
+    return true;
+  }
   case Intrinsic::prefetch: {
     Value *Addr = CI.getOperand(0);
     unsigned RW = cast<ConstantInt>(CI.getOperand(1))->getZExtValue();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
new file mode 100644
index 0000000000000..8ceac0dc21f2d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-sucmp.ll
@@ -0,0 +1,54 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -O0 -mtriple=aarch64-linux-gnu -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+
+define void @scmp_i32(i32 %arg1, i32 %arg2) {
+  ; CHECK-LABEL: name: scmp_i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $w0, $w1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+  ; CHECK-NEXT:   [[SCMP:%[0-9]+]]:_(s4) = G_SCMP [[COPY1]](s32), [[COPY1]]
+  ; CHECK-NEXT:   RET_ReallyLR
+  %res4 = call i4 @llvm.scmp.i4.i32(i32 %arg2, i32 %arg2)
+  ret void
+}
+
+define void @scmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) {
+  ; CHECK-LABEL: name: scmp_4_32i
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $q0, $q1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+  ; CHECK-NEXT:   [[SCMP:%[0-9]+]]:_(<4 x s32>) = G_SCMP [[COPY1]](<4 x s32>), [[COPY1]]
+  ; CHECK-NEXT:   RET_ReallyLR
+  %res4 = call <4 x i32> @llvm.scmp.v4i32.i32(<4 x i32> %arg2, <4 x i32> %arg2)
+  ret void
+}
+
+define void @ucmp_i32(i32 %arg1, i32 %arg2) {
+  ; CHECK-LABEL: name: ucmp_i32
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $w0, $w1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
+  ; CHECK-NEXT:   [[UCMP:%[0-9]+]]:_(s4) = G_UCMP [[COPY1]](s32), [[COPY1]]
+  ; CHECK-NEXT:   RET_ReallyLR
+  %res4 = call i4 @llvm.ucmp.i4.i32(i32 %arg2, i32 %arg2)
+  ret void
+}
+
+define void @ucmp_4_32i(<4 x i32> %arg1, <4 x i32> %arg2) {
+  ; CHECK-LABEL: name: ucmp_4_32i
+  ; CHECK: bb.1 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $q0, $q1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
+  ; CHECK-NEXT:   [[UCMP:%[0-9]+]]:_(<4 x s32>) = G_UCMP [[COPY1]](<4 x s32>), [[COPY1]]
+  ; CHECK-NEXT:   RET_ReallyLR
+  %res4 = call <4 x i32> @llvm.ucmp.v4i32.i32(<4 x i32> %arg2, <4 x i32> %arg2)
+  ret void
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/99518