[llvm] [instcombine] Pull sext/zext through reduce.or/and (PR #99394)

[Nikita Popov via llvm-commits]

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@@ -3356,24 +3349,40 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) {
       return II;
     }
 
-    if (match(Arg, m_ZExtOrSExtOrSelf(m_Value(Vect)))) {
-      if (auto *FTy = dyn_cast<FixedVectorType>(Vect->getType()))
-        if (FTy->getElementType() == Builder.getInt1Ty()) {
-          Value *Res = Builder.CreateBitCast(
-              Vect, Builder.getIntNTy(FTy->getNumElements()));
-          if (IID == Intrinsic::vector_reduce_and) {
-            Res = Builder.CreateICmpEQ(
-                Res, ConstantInt::getAllOnesValue(Res->getType()));
-          } else {
-            assert(IID == Intrinsic::vector_reduce_or &&
-                   "Expected or reduction.");
-            Res = Builder.CreateIsNotNull(Res);
-          }
-          if (Arg != Vect)
-            Res = Builder.CreateCast(cast<CastInst>(Arg)->getOpcode(), Res,
-                                     II->getType());
-          return replaceInstUsesWith(CI, Res);
-        }
+    // reduce_or (z/sext V) -> z/sext (reduce_or V)
+    // reduce_and (z/sext V) -> z/sext (reduce_and V)
+    if (match(Arg, m_ZExtOrSExt(m_Value(Vect)))) {
+      Value *Res;
+      if (IID == Intrinsic::vector_reduce_and) {
+        Res = Builder.CreateAndReduce(Vect);
+      } else {
+        assert(IID == Intrinsic::vector_reduce_or && "Expected or reduction.");
+        Res = Builder.CreateOrReduce(Vect);
+      }
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nikic wrote:

Create based on the intrinsic ID instead? No need for the if/else.

https://github.com/llvm/llvm-project/pull/99394