[llvm] 3e47f6b - Rapply "[Target] Use range-based for loops (NFC) (#98844)"
Kazu Hirata via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 17 19:39:10 PDT 2024
Author: Kazu Hirata
Date: 2024-07-17T19:39:04-07:00
New Revision: 3e47f6ba4a2aae7a8414dfeafa21d8d79e806c43
URL: https://github.com/llvm/llvm-project/commit/3e47f6ba4a2aae7a8414dfeafa21d8d79e806c43
DIFF: https://github.com/llvm/llvm-project/commit/3e47f6ba4a2aae7a8414dfeafa21d8d79e806c43.diff
LOG: Rapply "[Target] Use range-based for loops (NFC) (#98844)"
This iteration drops hunks where the loop body adds more elements.
Added:
Modified:
llvm/lib/Target/ARM/ARMFrameLowering.cpp
llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
llvm/lib/Target/Mips/MipsFastISel.cpp
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
llvm/lib/Target/PowerPC/PPCFastISel.cpp
llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
index 831b6b0fc7223..e94b0f6e1a44f 100644
--- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp
@@ -1673,8 +1673,8 @@ void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB,
.addReg(ARM::SP)
.add(predOps(ARMCC::AL))
.setMIFlags(MachineInstr::FrameDestroy);
- for (unsigned i = 0, e = Regs.size(); i < e; ++i)
- MIB.addReg(Regs[i], getDefRegState(true));
+ for (unsigned Reg : Regs)
+ MIB.addReg(Reg, getDefRegState(true));
if (DeleteRet) {
if (MI != MBB.end()) {
MIB.copyImplicitOps(*MI);
diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
index e5e817f1ed9a2..b55b9a42e52cd 100644
--- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -2579,8 +2579,8 @@ ARMPreAllocLoadStoreOpt::RescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
Bases.push_back(Base);
return;
}
- for (unsigned i = 0, e = BI->second.size(); i != e; ++i) {
- if (Offset == getMemoryOpOffset(*BI->second[i])) {
+ for (const MachineInstr *MI : BI->second) {
+ if (Offset == getMemoryOpOffset(*MI)) {
StopHere = true;
break;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 99745941d5798..6926b02701771 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -1056,8 +1056,8 @@ bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
continue;
B->erase(MI);
- for (unsigned i = 0, n = Regs.size(); i != n; ++i)
- MRI.markUsesInDebugValueAsUndef(Regs[i]);
+ for (unsigned Reg : Regs)
+ MRI.markUsesInDebugValueAsUndef(Reg);
Changed = true;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index a4304b0531666..8840c272057ab 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -1040,8 +1040,8 @@ void HexagonGenInsert::pruneEmptyLists() {
if (I->second.empty())
Prune.push_back(I);
}
- for (unsigned i = 0, n = Prune.size(); i < n; ++i)
- IFMap.erase(Prune[i]);
+ for (const auto &It : Prune)
+ IFMap.erase(It);
}
void HexagonGenInsert::pruneCoveredSets(unsigned VR) {
@@ -1470,8 +1470,8 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) {
continue;
B->erase(MI);
- for (unsigned I = 0, N = Regs.size(); I != N; ++I)
- MRI->markUsesInDebugValueAsUndef(Regs[I]);
+ for (unsigned Reg : Regs)
+ MRI->markUsesInDebugValueAsUndef(Reg);
Changed = true;
}
@@ -1582,8 +1582,8 @@ bool HexagonGenInsert::runOnMachineFunction(MachineFunction &MF) {
if (Idx >= Cutoff)
Out.push_back(I);
}
- for (unsigned i = 0, n = Out.size(); i < n; ++i)
- IFMap.erase(Out[i]);
+ for (const auto &It : Out)
+ IFMap.erase(It);
}
if (IFMap.empty())
return Changed;
diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index ec12af66ff2d4..bd8ef43da625c 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -1763,8 +1763,8 @@ bool MipsFastISel::selectRet(const Instruction *I) {
RetRegs.push_back(VA.getLocReg());
}
MachineInstrBuilder MIB = emitInst(Mips::RetRA);
- for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
- MIB.addReg(RetRegs[i], RegState::Implicit);
+ for (unsigned Reg : RetRegs)
+ MIB.addReg(Reg, RegState::Implicit);
return true;
}
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index d6e20932a247e..0b654abd2814c 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -861,8 +861,8 @@ void NVPTXAsmPrinter::emitGlobals(const Module &M) {
*static_cast<const NVPTXSubtarget *>(NTM.getSubtargetImpl());
// Print out module-level global variables in proper order
- for (unsigned i = 0, e = Globals.size(); i != e; ++i)
- printModuleLevelGV(Globals[i], OS2, /*processDemoted=*/false, STI);
+ for (const GlobalVariable *GV : Globals)
+ printModuleLevelGV(GV, OS2, /*processDemoted=*/false, STI);
OS2 << '\n';
diff --git a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
index ff3d36d39fb29..4c522e2c5be41 100644
--- a/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
+++ b/llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp
@@ -149,8 +149,8 @@ namespace {
Changed = true;
}
- for (unsigned i = 0, ie = PredToRemove.size(); i != ie; ++i)
- PredToRemove[i]->removeSuccessor(&ReturnMBB, true);
+ for (MachineBasicBlock *MBB : PredToRemove)
+ MBB->removeSuccessor(&ReturnMBB, true);
if (Changed && !ReturnMBB.hasAddressTaken()) {
// We now might be able to merge this blr-only block into its
diff --git a/llvm/lib/Target/PowerPC/PPCFastISel.cpp b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
index 0e04bb944c3bb..8d364bcb22394 100644
--- a/llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ b/llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -1668,8 +1668,8 @@ bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
}
// Add implicit physical register uses to the call.
- for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
- MIB.addReg(RegArgs[II], RegState::Implicit);
+ for (unsigned Reg : RegArgs)
+ MIB.addReg(Reg, RegState::Implicit);
// Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
// into the call.
@@ -1793,8 +1793,8 @@ bool PPCFastISel::SelectRet(const Instruction *I) {
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD,
TII.get(PPC::BLR8));
- for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
- MIB.addReg(RetRegs[i], RegState::Implicit);
+ for (unsigned Reg : RetRegs)
+ MIB.addReg(Reg, RegState::Implicit);
return true;
}
diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
index 8a74d77e369f6..7dc5c099c1270 100644
--- a/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
+++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegColoring.cpp
@@ -135,8 +135,7 @@ static void undefInvalidDbgValues(
#ifndef NDEBUG
DenseSet<Register> SeenRegs;
#endif
- for (size_t I = 0, E = Assignments.size(); I < E; ++I) {
- const auto &CoalescedIntervals = Assignments[I];
+ for (const auto &CoalescedIntervals : Assignments) {
if (CoalescedIntervals.empty())
continue;
for (LiveInterval *LI : CoalescedIntervals) {
diff --git a/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp b/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
index 793e624eefa8a..95962d1a0a240 100644
--- a/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
+++ b/llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp
@@ -178,8 +178,7 @@ bool XCoreLowerThreadLocal::runOnModule(Module &M) {
for (GlobalVariable &GV : M.globals())
if (GV.isThreadLocal())
ThreadLocalGlobals.push_back(&GV);
- for (unsigned I = 0, E = ThreadLocalGlobals.size(); I != E; ++I) {
- MadeChange |= lowerGlobal(ThreadLocalGlobals[I]);
- }
+ for (GlobalVariable *GV : ThreadLocalGlobals)
+ MadeChange |= lowerGlobal(GV);
return MadeChange;
}
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