[llvm] 495d3ea - [MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)

[via llvm-commits]

Author: Craig Topper
Date: 2024-07-17T13:06:58-07:00
New Revision: 495d3ea989d4e97ce77ee73d6b35b171a7346019

URL: https://github.com/llvm/llvm-project/commit/495d3ea989d4e97ce77ee73d6b35b171a7346019
DIFF: https://github.com/llvm/llvm-project/commit/495d3ea989d4e97ce77ee73d6b35b171a7346019.diff

LOG: [MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)

The included test case contains X0 as a def register. X0 is considered a
constant register when it is a use. When its a def, it means to throw
away the result value.

If we treat it as a constant register here, we will execute the continue
and not assign `DefReg` to any register. This will cause a crash when
trying to get the register class for `DefReg` after the loop.

By only checking isConstantPhysReg for uses, we will reach the `return
false` a little further down and stop processing this instruction.

Added: 
    llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir

Modified: 
    llvm/lib/CodeGen/MachineSink.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index d782c8b086319..4b3ff57fb478a 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -417,7 +417,7 @@ bool MachineSinking::PerformSinkAndFold(MachineInstr &MI,
       continue;
     }
 
-    if (Reg.isPhysical() &&
+    if (Reg.isPhysical() && MO.isUse() &&
         (MRI->isConstantPhysReg(Reg) || TII->isIgnorableUse(MO)))
       continue;
 

diff  --git a/llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir b/llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir
new file mode 100644
index 0000000000000..a14c5ceed9ec5
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/sink-and-fold-crash.mir
@@ -0,0 +1,39 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc %s -mtriple=riscv64 -run-pass=machine-sink -o - | FileCheck %s
+
+---
+name:            main
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: fpr32 }
+  - { id: 1, class: fpr32 }
+  - { id: 2, class: gpr }
+  - { id: 3, class: gpr }
+liveins:
+  - { reg: '$f10_f', virtual-reg: '%0' }
+  - { reg: '$f11_f', virtual-reg: '%1' }
+body:             |
+  bb.0.entry:
+    liveins: $f10_f, $f11_f
+
+    ; CHECK-LABEL: name: main
+    ; CHECK: liveins: $f10_f, $f11_f
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $f11_f
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $f10_f
+    ; CHECK-NEXT: [[ReadFFLAGS:%[0-9]+]]:gpr = ReadFFLAGS implicit $fflags
+    ; CHECK-NEXT: [[FLE_S:%[0-9]+]]:gpr = nofpexcept FLE_S [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: WriteFFLAGS killed [[ReadFFLAGS]], implicit-def $fflags
+    ; CHECK-NEXT: $x0 = nofpexcept FEQ_S [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x10 = COPY [[FLE_S]]
+    ; CHECK-NEXT: PseudoRET implicit $x10
+    %1:fpr32 = COPY $f11_f
+    %0:fpr32 = COPY $f10_f
+    %3:gpr = ReadFFLAGS implicit $fflags
+    %2:gpr = nofpexcept FLE_S %0, %1
+    WriteFFLAGS killed %3, implicit-def $fflags
+    $x0 = nofpexcept FEQ_S %0, %1
+    $x10 = COPY %2
+    PseudoRET implicit $x10
+
+...