[llvm] [AArch64] Lower scalable i1 vector add reduction to cntp (PR #99031)
Max Beck-Jones via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 17 09:16:58 PDT 2024
================
@@ -27469,6 +27469,21 @@ SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,
VecOp = convertToScalableVector(DAG, ContainerVT, VecOp);
}
+ // Lower VECREDUCE_ADD of nxv2i1-nxv16i1 to CNTP rather than UADDV.
+ if (ScalarOp.getOpcode() == ISD::VECREDUCE_ADD &&
+ VecOp.getOpcode() == ISD::ZERO_EXTEND) {
+ SDValue Vec = VecOp.getOperand(0);
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DevM-uk wrote:
Looks clearer to me.
https://github.com/llvm/llvm-project/pull/99031
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