[llvm] [AArch64] Lower scalable i1 vector add reduction to cntp (PR #99031)

[Max Beck-Jones via llvm-commits]

================
@@ -27469,6 +27469,21 @@ SDValue AArch64TargetLowering::LowerReductionToSVE(unsigned Opcode,
     VecOp = convertToScalableVector(DAG, ContainerVT, VecOp);
   }
 
+  // Lower VECREDUCE_ADD of nxv2i1-nxv16i1 to CNTP rather than UADDV.
+  if (ScalarOp.getOpcode() == ISD::VECREDUCE_ADD &&
+      VecOp.getOpcode() == ISD::ZERO_EXTEND) {
+    SDValue Vec = VecOp.getOperand(0);
+    EVT VecVT = Vec.getValueType();
+    if (VecVT.getVectorElementType() == MVT::i1) {
----------------
DevM-uk wrote:

I thought that all types have already been legalised and therefore any scalable i1 vector is a legal predicate type.
Starting with a `<vscale x 32 x i1>` results in it getting split into two `nxv16i1`s which are then zero extended and added together before being add reduced. I don't match this so it gets lowered to a `UADDV_PRED`.

https://github.com/llvm/llvm-project/pull/99031