[llvm] [AArch64][SVE] Improve code quality of vector unsigned/signed add reductions. (PR #97339)

[Dinar Temirbulatov via llvm-commits]

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@@ -17455,6 +17456,77 @@ static SDValue performVecReduceAddCombineWithUADDLP(SDNode *N,
   return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP);
 }
 
+// Turn [sign|zero]_extend(vecreduce_add()) into SVE's  SADDV|UADDV
+// instructions.
+static SDValue
+performVecReduceAddExtCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
+                              const AArch64TargetLowering &TLI) {
+  if (N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
+      N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND)
+    return SDValue();
+  bool IsSigned = N->getOperand(0).getOpcode() == ISD::SIGN_EXTEND;
+
+  SelectionDAG &DAG = DCI.DAG;
+  auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
+  SDValue VecOp = N->getOperand(0).getOperand(0);
+  SDLoc DL(N);
+
+  bool IsScalableType = VecOp.getValueType().isScalableVector();
+  std::deque<SDValue> ResultValues;
+  ResultValues.push_back(VecOp);
+
+  // Split the input vectors if not legal.
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dtemirbulatov wrote:

Done.

https://github.com/llvm/llvm-project/pull/97339