[llvm] [SLP][REVEC] Make Instruction::Call support vector instructions. (PR #99317)

[Han-Kuan Chen via llvm-commits]

https://github.com/HanKuanChen created https://github.com/llvm/llvm-project/pull/99317

None

>From 3b4233214a04e52097c66a41b275d2c77e1a6e80 Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Fri, 28 Jun 2024 00:14:45 -0700
Subject: [PATCH 1/2] [SLP][REVEC] Pre-commit test.

---
 llvm/test/Transforms/SLPVectorizer/revec.ll | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/llvm/test/Transforms/SLPVectorizer/revec.ll b/llvm/test/Transforms/SLPVectorizer/revec.ll
index 4b37b100763a9..eb9a7085926dd 100644
--- a/llvm/test/Transforms/SLPVectorizer/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/revec.ll
@@ -38,3 +38,16 @@ entry:
   store <4 x i32> %add.i65, ptr %arrayidx42, align 4
   ret void
 }
+
+define void @test2(ptr %in, ptr %out) {
+entry:
+  %0 = getelementptr i16, ptr %in, i64 8
+  %1 = load <8 x i16>, ptr %in, align 2
+  %2 = load <8 x i16>, ptr %0, align 2
+  %3 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %1, <8 x i16> %1)
+  %4 = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %2, <8 x i16> %2)
+  %5 = getelementptr i16, ptr %out, i64 8
+  store <8 x i16> %3, ptr %out, align 2
+  store <8 x i16> %4, ptr %5, align 2
+  ret void
+}

>From b69609688156e842f70888c859e3cdfa8892747b Mon Sep 17 00:00:00 2001
From: Han-Kuan Chen <hankuan.chen at sifive.com>
Date: Fri, 28 Jun 2024 00:15:45 -0700
Subject: [PATCH 2/2] [SLP][REVEC] Make Instruction::Call support vector
 instructions.

---
 llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +-
 llvm/test/Transforms/SLPVectorizer/revec.ll     | 7 +++++++
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index ccb6734d5618c..595cd3b558b52 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -13498,7 +13498,7 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) {
         }
         ScalarArg = CEI->getArgOperand(I);
         if (cast<VectorType>(OpVec->getType())->getElementType() !=
-                ScalarArg->getType() &&
+                ScalarArg->getType()->getScalarType() &&
             It == MinBWs.end()) {
           auto *CastTy =
               getWidenedType(ScalarArg->getType(), VecTy->getNumElements());
diff --git a/llvm/test/Transforms/SLPVectorizer/revec.ll b/llvm/test/Transforms/SLPVectorizer/revec.ll
index eb9a7085926dd..c2dc6d0ab73b7 100644
--- a/llvm/test/Transforms/SLPVectorizer/revec.ll
+++ b/llvm/test/Transforms/SLPVectorizer/revec.ll
@@ -40,6 +40,13 @@ entry:
 }
 
 define void @test2(ptr %in, ptr %out) {
+; CHECK-LABEL: @test2(
+; CHECK-NEXT:  entry:
+; CHECK-NEXT:    [[TMP0:%.*]] = load <16 x i16>, ptr [[IN:%.*]], align 2
+; CHECK-NEXT:    [[TMP1:%.*]] = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> [[TMP0]], <16 x i16> [[TMP0]])
+; CHECK-NEXT:    store <16 x i16> [[TMP1]], ptr [[OUT:%.*]], align 2
+; CHECK-NEXT:    ret void
+;
 entry:
   %0 = getelementptr i16, ptr %in, i64 8
   %1 = load <8 x i16>, ptr %in, align 2