[llvm] 2901848 - Revert "[AArch64] Remove superfluous sxtw in peephole opt (#96293)"
Krasimir Georgiev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 17 03:56:40 PDT 2024
Author: Krasimir Georgiev
Date: 2024-07-17T10:53:25Z
New Revision: 290184880ae22541738e280397da33fe515e4c86
URL: https://github.com/llvm/llvm-project/commit/290184880ae22541738e280397da33fe515e4c86
DIFF: https://github.com/llvm/llvm-project/commit/290184880ae22541738e280397da33fe515e4c86.diff
LOG: Revert "[AArch64] Remove superfluous sxtw in peephole opt (#96293)"
This reverts commit 7f2a5dfe35f8bbaca2819644c7aa844f938befd6.
It appears that after this, llc segfaults on the following code:
```
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64--linux-eabi"
define i32 @f(i32 %0) {
entry:
%1 = sext i32 %0 to i64
br label %A
A:
%2 = trunc i64 %1 to i32
%a69.us = sub i32 0, %2
%a69.us.fr = freeze i32 %a69.us
%3 = zext i32 %a69.us.fr to i64
br label %B
B:
%t = icmp eq i64 0, %3
br i1 %t, label %A, label %B
}
```
assert.h assertion failed at .../llvm/lib/CodeGen/LiveVariables.cpp:159 in void llvm::LiveVariables::HandleVirtRegUse(Register, MachineBasicBlock *, MachineInstr &): MRI->getVRegDef(Reg) && "Register use before def!"
Added:
Modified:
llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
Removed:
llvm/lib/Target/AArch64/peephole-sxtw.mir
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index a758e0d3e7b55..bd11bc4dd6e3f 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -128,7 +128,6 @@ struct AArch64MIPeepholeOpt : public MachineFunctionPass {
bool visitINSviGPR(MachineInstr &MI, unsigned Opc);
bool visitINSvi64lane(MachineInstr &MI);
bool visitFMOVDr(MachineInstr &MI);
- bool visitCopy(MachineInstr &MI);
bool runOnMachineFunction(MachineFunction &MF) override;
StringRef getPassName() const override {
@@ -691,34 +690,6 @@ bool AArch64MIPeepholeOpt::visitFMOVDr(MachineInstr &MI) {
return true;
}
-// Across a basic-block we might have in i32 extract from a value that only
-// operates on upper bits (for example a sxtw). We can replace the COPY with a
-// new version skipping the sxtw.
-bool AArch64MIPeepholeOpt::visitCopy(MachineInstr &MI) {
- Register InputReg = MI.getOperand(1).getReg();
- if (MI.getOperand(1).getSubReg() != AArch64::sub_32 ||
- !MRI->hasOneNonDBGUse(InputReg))
- return false;
-
- MachineInstr *SrcMI = MRI->getUniqueVRegDef(InputReg);
- MachineInstr *CopyMI = SrcMI;
- while (SrcMI && SrcMI->isFullCopy() &&
- MRI->hasOneNonDBGUse(SrcMI->getOperand(1).getReg()))
- SrcMI = MRI->getUniqueVRegDef(SrcMI->getOperand(1).getReg());
-
- if (!SrcMI || SrcMI->getOpcode() != AArch64::SBFMXri ||
- SrcMI->getOperand(2).getImm() != 0 || SrcMI->getOperand(3).getImm() != 31)
- return false;
-
- Register SrcReg = SrcMI->getOperand(1).getReg();
- MRI->constrainRegClass(SrcReg, MRI->getRegClass(InputReg));
- MI.getOperand(1).setReg(SrcReg);
- if (CopyMI != SrcMI)
- CopyMI->eraseFromParent();
- SrcMI->eraseFromParent();
- return true;
-}
-
bool AArch64MIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
@@ -800,9 +771,6 @@ bool AArch64MIPeepholeOpt::runOnMachineFunction(MachineFunction &MF) {
case AArch64::FMOVDr:
Changed |= visitFMOVDr(MI);
break;
- case AArch64::COPY:
- Changed |= visitCopy(MI);
- break;
}
}
}
diff --git a/llvm/lib/Target/AArch64/peephole-sxtw.mir b/llvm/lib/Target/AArch64/peephole-sxtw.mir
deleted file mode 100644
index 6dd91fbf6ec1d..0000000000000
--- a/llvm/lib/Target/AArch64/peephole-sxtw.mir
+++ /dev/null
@@ -1,46 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -run-pass=aarch64-mi-peephole-opt -o - -mtriple=aarch64-unknown-linux -verify-machineinstrs %s | FileCheck %s
-
----
-name: removeSxtw
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x0
- ; CHECK-LABEL: name: removeSxtw
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
- ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY1]], 1, 0
- ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
- ; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr64 = COPY $x0
- %1:gpr64 = SBFMXri %0:gpr64, 0, 31
- %2:gpr32sp = COPY %1.sub_32:gpr64
- %3:gpr32sp = ADDWri %2:gpr32sp, 1, 0
- $w0 = COPY %3:gpr32sp
- RET_ReallyLR implicit $w0
-...
----
-name: extraCopy
-tracksRegLiveness: true
-body: |
- bb.0.entry:
- liveins: $x0
- ; CHECK-LABEL: name: extraCopy
- ; CHECK: liveins: $x0
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32sp = COPY [[COPY]].sub_32
- ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY1]], 1, 0
- ; CHECK-NEXT: $w0 = COPY [[ADDWri]]
- ; CHECK-NEXT: RET_ReallyLR implicit $w0
- %0:gpr64 = COPY $x0
- %1:gpr64 = SBFMXri %0:gpr64, 0, 31
- %2:gpr64all = COPY %1:gpr64
- %3:gpr32sp = COPY %2.sub_32:gpr64all
- %4:gpr32sp = ADDWri %3:gpr32sp, 1, 0
- $w0 = COPY %4:gpr32sp
- RET_ReallyLR implicit $w0
-...
diff --git a/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll b/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
index f49d469e50cdd..9b0701ab148dc 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
@@ -281,7 +281,8 @@ define i64 @smull_ldrsw_shift(ptr %x0, i64 %x1) {
; CHECK-LABEL: smull_ldrsw_shift:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsw x8, [x0]
-; CHECK-NEXT: smull x0, w8, w1
+; CHECK-NEXT: sxtw x9, w1
+; CHECK-NEXT: smull x0, w8, w9
; CHECK-NEXT: ret
entry:
%ext64 = load i32, ptr %x0
@@ -489,7 +490,8 @@ define i64 @smaddl_ldrsw_shift(ptr %x0, i64 %x1, i64 %x2) {
; CHECK-LABEL: smaddl_ldrsw_shift:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsw x8, [x0]
-; CHECK-NEXT: smaddl x0, w8, w1, x2
+; CHECK-NEXT: sxtw x9, w1
+; CHECK-NEXT: smaddl x0, w8, w9, x2
; CHECK-NEXT: ret
entry:
%ext64 = load i32, ptr %x0
@@ -652,7 +654,8 @@ define i64 @smnegl_ldrsw_shift(ptr %x0, i64 %x1) {
; CHECK-LABEL: smnegl_ldrsw_shift:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsw x8, [x0]
-; CHECK-NEXT: smnegl x0, w8, w1
+; CHECK-NEXT: sxtw x9, w1
+; CHECK-NEXT: smnegl x0, w8, w9
; CHECK-NEXT: ret
entry:
%ext64 = load i32, ptr %x0
@@ -815,7 +818,8 @@ define i64 @smsubl_ldrsw_shift(ptr %x0, i64 %x1, i64 %x2) {
; CHECK-LABEL: smsubl_ldrsw_shift:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ldrsw x8, [x0]
-; CHECK-NEXT: smsubl x0, w8, w1, x2
+; CHECK-NEXT: sxtw x9, w1
+; CHECK-NEXT: smsubl x0, w8, w9, x2
; CHECK-NEXT: ret
entry:
%ext64 = load i32, ptr %x0
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