[llvm] 8ca7e24 - [RISCV] Add more vector setcc VI isel patterns.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 22:01:28 PDT 2024
Author: Craig Topper
Date: 2024-07-16T22:01:18-07:00
New Revision: 8ca7e24b359ab2b6d2868f9252c7cd11eb48c787
URL: https://github.com/llvm/llvm-project/commit/8ca7e24b359ab2b6d2868f9252c7cd11eb48c787
DIFF: https://github.com/llvm/llvm-project/commit/8ca7e24b359ab2b6d2868f9252c7cd11eb48c787.diff
LOG: [RISCV] Add more vector setcc VI isel patterns.
Add more patterns isel patterns for vmseq.vi and friends with
the constant splat on the left hand side.
We can't trust the canonicalization in SimplifySetCC to keep constants
to the RHS when the splat is VMV_V_X_VL for i64 on RV32.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index a0f37ea4c6fea..7afd6def4e4d2 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -306,21 +306,6 @@ multiclass VPatIntegerSetCCSDNode_VV_Swappable<string instruction_name,
}
}
-multiclass VPatIntegerSetCCSDNode_XI<
- string instruction_name,
- CondCode cc,
- string kind,
- ComplexPattern SplatPatKind,
- DAGOperand xop_kind> {
- foreach vti = AllIntegerVectors in {
- defvar instruction = !cast<Instruction>(instruction_name#_#kind#_#vti.LMul.MX);
- let Predicates = GetVTypePredicates<vti>.Predicates in
- def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
- (vti.Vector (SplatPatKind (XLenVT xop_kind:$rs2))), cc)),
- (instruction vti.RegClass:$rs1, xop_kind:$rs2, vti.AVL, vti.Log2SEW)>;
- }
-}
-
multiclass VPatIntegerSetCCSDNode_XI_Swappable<string instruction_name,
CondCode cc, CondCode invcc,
string kind,
@@ -344,19 +329,28 @@ multiclass VPatIntegerSetCCSDNode_VX_Swappable<string instruction_name,
: VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VX",
SplatPat, GPR>;
-multiclass VPatIntegerSetCCSDNode_VI<string instruction_name, CondCode cc>
- : VPatIntegerSetCCSDNode_XI<instruction_name, cc, "VI", SplatPat_simm5, simm5>;
+multiclass VPatIntegerSetCCSDNode_VI_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc>
+ : VPatIntegerSetCCSDNode_XI_Swappable<instruction_name, cc, invcc, "VI",
+ SplatPat_simm5, simm5>;
-multiclass VPatIntegerSetCCSDNode_VIPlus1<string instruction_name, CondCode cc,
- ComplexPattern splatpat_kind> {
+multiclass VPatIntegerSetCCSDNode_VIPlus1_Swappable<string instruction_name,
+ CondCode cc, CondCode invcc,
+ ComplexPattern splatpat_kind> {
foreach vti = AllIntegerVectors in {
defvar instruction = !cast<Instruction>(instruction_name#"_VI_"#vti.LMul.MX);
- let Predicates = GetVTypePredicates<vti>.Predicates in
- def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
- (vti.Vector (splatpat_kind simm5:$rs2)),
- cc)),
- (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
- vti.AVL, vti.Log2SEW)>;
+ let Predicates = GetVTypePredicates<vti>.Predicates in {
+ def : Pat<(vti.Mask (setcc (vti.Vector vti.RegClass:$rs1),
+ (vti.Vector (splatpat_kind simm5:$rs2)),
+ cc)),
+ (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
+ vti.AVL, vti.Log2SEW)>;
+ def : Pat<(vti.Mask (setcc (vti.Vector (splatpat_kind simm5:$rs2)),
+ (vti.Vector vti.RegClass:$rs1),
+ invcc)),
+ (instruction vti.RegClass:$rs1, (DecImm simm5:$rs2),
+ vti.AVL, vti.Log2SEW)>;
+ }
}
}
@@ -1045,21 +1039,21 @@ defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGT", SETGT, SETLT>;
defm : VPatIntegerSetCCSDNode_VX_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
// There is no VMSGE(U)_VX instruction
-defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSEQ", SETEQ>;
-defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSNE", SETNE>;
-defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLE", SETLE>;
-defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSLEU", SETULE>;
-defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGT", SETGT>;
-defm : VPatIntegerSetCCSDNode_VI<"PseudoVMSGTU", SETUGT>;
-
-defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLE", SETLT,
- SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSLEU", SETULT,
- SplatPat_simm5_plus1_nonzero>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGT", SETGE,
- SplatPat_simm5_plus1>;
-defm : VPatIntegerSetCCSDNode_VIPlus1<"PseudoVMSGTU", SETUGE,
- SplatPat_simm5_plus1_nonzero>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSEQ", SETEQ, SETEQ>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSNE", SETNE, SETNE>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLE", SETLE, SETGE>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSLEU", SETULE, SETUGE>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGT", SETGT, SETLT>;
+defm : VPatIntegerSetCCSDNode_VI_Swappable<"PseudoVMSGTU", SETUGT, SETULT>;
+
+defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLE", SETLT, SETGT,
+ SplatPat_simm5_plus1>;
+defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSLEU", SETULT, SETUGT,
+ SplatPat_simm5_plus1_nonzero>;
+defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGT", SETGE, SETLE,
+ SplatPat_simm5_plus1>;
+defm : VPatIntegerSetCCSDNode_VIPlus1_Swappable<"PseudoVMSGTU", SETUGE, SETULE,
+ SplatPat_simm5_plus1_nonzero>;
// 11.9. Vector Integer Min/Max Instructions
defm : VPatBinarySDNode_VV_VX<umin, "PseudoVMINU">;
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 479664c6f5f62..50bbe4f7b4c2d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -1216,19 +1216,19 @@ define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
; RV32F-LABEL: cttz_nxv1i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v9, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v9
+; RV32F-NEXT: vand.vv v9, v8, v9
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v9, v8
-; RV32F-NEXT: vsrl.vi v8, v9, 23
+; RV32F-NEXT: vfncvt.f.xu.w v10, v9
+; RV32F-NEXT: vsrl.vi v9, v10, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vzext.vf2 v9, v8
+; RV32F-NEXT: vzext.vf2 v10, v9
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v9, a1
+; RV32F-NEXT: vsub.vx v9, v10, a1
+; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vmerge.vxm v8, v9, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1250,39 +1250,22 @@ define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
-; RV32D-LABEL: cttz_nxv1i64:
-; RV32D: # %bb.0:
-; RV32D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV32D-NEXT: vmseq.vx v0, v8, zero
-; RV32D-NEXT: vrsub.vi v9, v8, 0
-; RV32D-NEXT: vand.vv v8, v8, v9
-; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v8, v8
-; RV32D-NEXT: li a1, 52
-; RV32D-NEXT: vsrl.vx v8, v8, a1
-; RV32D-NEXT: li a1, 1023
-; RV32D-NEXT: vsub.vx v8, v8, a1
-; RV32D-NEXT: li a1, 64
-; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
-; RV32D-NEXT: fsrm a0
-; RV32D-NEXT: ret
-;
-; RV64D-LABEL: cttz_nxv1i64:
-; RV64D: # %bb.0:
-; RV64D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV64D-NEXT: vrsub.vi v9, v8, 0
-; RV64D-NEXT: vand.vv v9, v8, v9
-; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v9, v9
-; RV64D-NEXT: li a1, 52
-; RV64D-NEXT: vsrl.vx v9, v9, a1
-; RV64D-NEXT: li a1, 1023
-; RV64D-NEXT: vsub.vx v9, v9, a1
-; RV64D-NEXT: vmseq.vi v0, v8, 0
-; RV64D-NEXT: li a1, 64
-; RV64D-NEXT: vmerge.vxm v8, v9, a1, v0
-; RV64D-NEXT: fsrm a0
-; RV64D-NEXT: ret
+; CHECK-D-LABEL: cttz_nxv1i64:
+; CHECK-D: # %bb.0:
+; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-D-NEXT: vrsub.vi v9, v8, 0
+; CHECK-D-NEXT: vand.vv v9, v8, v9
+; CHECK-D-NEXT: fsrmi a0, 1
+; CHECK-D-NEXT: vfcvt.f.xu.v v9, v9
+; CHECK-D-NEXT: li a1, 52
+; CHECK-D-NEXT: vsrl.vx v9, v9, a1
+; CHECK-D-NEXT: li a1, 1023
+; CHECK-D-NEXT: vsub.vx v9, v9, a1
+; CHECK-D-NEXT: vmseq.vi v0, v8, 0
+; CHECK-D-NEXT: li a1, 64
+; CHECK-D-NEXT: vmerge.vxm v8, v9, a1, v0
+; CHECK-D-NEXT: fsrm a0
+; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv1i64:
; CHECK-ZVBB: # %bb.0:
@@ -1378,19 +1361,19 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV32F-LABEL: cttz_nxv2i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v10, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v10
+; RV32F-NEXT: vand.vv v10, v8, v10
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: vsrl.vi v8, v10, 23
+; RV32F-NEXT: vfncvt.f.xu.w v12, v10
+; RV32F-NEXT: vsrl.vi v10, v12, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vzext.vf2 v10, v8
+; RV32F-NEXT: vzext.vf2 v12, v10
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v10, a1
+; RV32F-NEXT: vsub.vx v10, v12, a1
+; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vmerge.vxm v8, v10, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1412,39 +1395,22 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
-; RV32D-LABEL: cttz_nxv2i64:
-; RV32D: # %bb.0:
-; RV32D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; RV32D-NEXT: vmseq.vx v0, v8, zero
-; RV32D-NEXT: vrsub.vi v10, v8, 0
-; RV32D-NEXT: vand.vv v8, v8, v10
-; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v8, v8
-; RV32D-NEXT: li a1, 52
-; RV32D-NEXT: vsrl.vx v8, v8, a1
-; RV32D-NEXT: li a1, 1023
-; RV32D-NEXT: vsub.vx v8, v8, a1
-; RV32D-NEXT: li a1, 64
-; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
-; RV32D-NEXT: fsrm a0
-; RV32D-NEXT: ret
-;
-; RV64D-LABEL: cttz_nxv2i64:
-; RV64D: # %bb.0:
-; RV64D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; RV64D-NEXT: vrsub.vi v10, v8, 0
-; RV64D-NEXT: vand.vv v10, v8, v10
-; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v10, v10
-; RV64D-NEXT: li a1, 52
-; RV64D-NEXT: vsrl.vx v10, v10, a1
-; RV64D-NEXT: li a1, 1023
-; RV64D-NEXT: vsub.vx v10, v10, a1
-; RV64D-NEXT: vmseq.vi v0, v8, 0
-; RV64D-NEXT: li a1, 64
-; RV64D-NEXT: vmerge.vxm v8, v10, a1, v0
-; RV64D-NEXT: fsrm a0
-; RV64D-NEXT: ret
+; CHECK-D-LABEL: cttz_nxv2i64:
+; CHECK-D: # %bb.0:
+; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-D-NEXT: vrsub.vi v10, v8, 0
+; CHECK-D-NEXT: vand.vv v10, v8, v10
+; CHECK-D-NEXT: fsrmi a0, 1
+; CHECK-D-NEXT: vfcvt.f.xu.v v10, v10
+; CHECK-D-NEXT: li a1, 52
+; CHECK-D-NEXT: vsrl.vx v10, v10, a1
+; CHECK-D-NEXT: li a1, 1023
+; CHECK-D-NEXT: vsub.vx v10, v10, a1
+; CHECK-D-NEXT: vmseq.vi v0, v8, 0
+; CHECK-D-NEXT: li a1, 64
+; CHECK-D-NEXT: vmerge.vxm v8, v10, a1, v0
+; CHECK-D-NEXT: fsrm a0
+; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv2i64:
; CHECK-ZVBB: # %bb.0:
@@ -1540,19 +1506,19 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV32F-LABEL: cttz_nxv4i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v12, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v12
+; RV32F-NEXT: vand.vv v12, v8, v12
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v8
-; RV32F-NEXT: vsrl.vi v8, v12, 23
+; RV32F-NEXT: vfncvt.f.xu.w v16, v12
+; RV32F-NEXT: vsrl.vi v12, v16, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; RV32F-NEXT: vzext.vf2 v12, v8
+; RV32F-NEXT: vzext.vf2 v16, v12
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v12, a1
+; RV32F-NEXT: vsub.vx v12, v16, a1
+; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vmerge.vxm v8, v12, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1574,39 +1540,22 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
-; RV32D-LABEL: cttz_nxv4i64:
-; RV32D: # %bb.0:
-; RV32D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32D-NEXT: vmseq.vx v0, v8, zero
-; RV32D-NEXT: vrsub.vi v12, v8, 0
-; RV32D-NEXT: vand.vv v8, v8, v12
-; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v8, v8
-; RV32D-NEXT: li a1, 52
-; RV32D-NEXT: vsrl.vx v8, v8, a1
-; RV32D-NEXT: li a1, 1023
-; RV32D-NEXT: vsub.vx v8, v8, a1
-; RV32D-NEXT: li a1, 64
-; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
-; RV32D-NEXT: fsrm a0
-; RV32D-NEXT: ret
-;
-; RV64D-LABEL: cttz_nxv4i64:
-; RV64D: # %bb.0:
-; RV64D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64D-NEXT: vrsub.vi v12, v8, 0
-; RV64D-NEXT: vand.vv v12, v8, v12
-; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v12, v12
-; RV64D-NEXT: li a1, 52
-; RV64D-NEXT: vsrl.vx v12, v12, a1
-; RV64D-NEXT: li a1, 1023
-; RV64D-NEXT: vsub.vx v12, v12, a1
-; RV64D-NEXT: vmseq.vi v0, v8, 0
-; RV64D-NEXT: li a1, 64
-; RV64D-NEXT: vmerge.vxm v8, v12, a1, v0
-; RV64D-NEXT: fsrm a0
-; RV64D-NEXT: ret
+; CHECK-D-LABEL: cttz_nxv4i64:
+; CHECK-D: # %bb.0:
+; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-D-NEXT: vrsub.vi v12, v8, 0
+; CHECK-D-NEXT: vand.vv v12, v8, v12
+; CHECK-D-NEXT: fsrmi a0, 1
+; CHECK-D-NEXT: vfcvt.f.xu.v v12, v12
+; CHECK-D-NEXT: li a1, 52
+; CHECK-D-NEXT: vsrl.vx v12, v12, a1
+; CHECK-D-NEXT: li a1, 1023
+; CHECK-D-NEXT: vsub.vx v12, v12, a1
+; CHECK-D-NEXT: vmseq.vi v0, v8, 0
+; CHECK-D-NEXT: li a1, 64
+; CHECK-D-NEXT: vmerge.vxm v8, v12, a1, v0
+; CHECK-D-NEXT: fsrm a0
+; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv4i64:
; CHECK-ZVBB: # %bb.0:
@@ -1702,19 +1651,19 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV32F-LABEL: cttz_nxv8i64:
; RV32F: # %bb.0:
; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV32F-NEXT: vmseq.vx v0, v8, zero
; RV32F-NEXT: vrsub.vi v16, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v16
+; RV32F-NEXT: vand.vv v16, v8, v16
; RV32F-NEXT: fsrmi a0, 1
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v16, v8
-; RV32F-NEXT: vsrl.vi v8, v16, 23
+; RV32F-NEXT: vfncvt.f.xu.w v24, v16
+; RV32F-NEXT: vsrl.vi v16, v24, 23
; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32F-NEXT: vzext.vf2 v16, v8
+; RV32F-NEXT: vzext.vf2 v24, v16
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v16, a1
+; RV32F-NEXT: vsub.vx v16, v24, a1
+; RV32F-NEXT: vmseq.vi v0, v8, 0
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vmerge.vxm v8, v16, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1736,39 +1685,22 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64F-NEXT: fsrm a0
; RV64F-NEXT: ret
;
-; RV32D-LABEL: cttz_nxv8i64:
-; RV32D: # %bb.0:
-; RV32D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV32D-NEXT: vmseq.vx v0, v8, zero
-; RV32D-NEXT: vrsub.vi v16, v8, 0
-; RV32D-NEXT: vand.vv v8, v8, v16
-; RV32D-NEXT: fsrmi a0, 1
-; RV32D-NEXT: vfcvt.f.xu.v v8, v8
-; RV32D-NEXT: li a1, 52
-; RV32D-NEXT: vsrl.vx v8, v8, a1
-; RV32D-NEXT: li a1, 1023
-; RV32D-NEXT: vsub.vx v8, v8, a1
-; RV32D-NEXT: li a1, 64
-; RV32D-NEXT: vmerge.vxm v8, v8, a1, v0
-; RV32D-NEXT: fsrm a0
-; RV32D-NEXT: ret
-;
-; RV64D-LABEL: cttz_nxv8i64:
-; RV64D: # %bb.0:
-; RV64D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV64D-NEXT: vrsub.vi v16, v8, 0
-; RV64D-NEXT: vand.vv v16, v8, v16
-; RV64D-NEXT: fsrmi a0, 1
-; RV64D-NEXT: vfcvt.f.xu.v v16, v16
-; RV64D-NEXT: li a1, 52
-; RV64D-NEXT: vsrl.vx v16, v16, a1
-; RV64D-NEXT: li a1, 1023
-; RV64D-NEXT: vsub.vx v16, v16, a1
-; RV64D-NEXT: vmseq.vi v0, v8, 0
-; RV64D-NEXT: li a1, 64
-; RV64D-NEXT: vmerge.vxm v8, v16, a1, v0
-; RV64D-NEXT: fsrm a0
-; RV64D-NEXT: ret
+; CHECK-D-LABEL: cttz_nxv8i64:
+; CHECK-D: # %bb.0:
+; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-D-NEXT: vrsub.vi v16, v8, 0
+; CHECK-D-NEXT: vand.vv v16, v8, v16
+; CHECK-D-NEXT: fsrmi a0, 1
+; CHECK-D-NEXT: vfcvt.f.xu.v v16, v16
+; CHECK-D-NEXT: li a1, 52
+; CHECK-D-NEXT: vsrl.vx v16, v16, a1
+; CHECK-D-NEXT: li a1, 1023
+; CHECK-D-NEXT: vsub.vx v16, v16, a1
+; CHECK-D-NEXT: vmseq.vi v0, v8, 0
+; CHECK-D-NEXT: li a1, 64
+; CHECK-D-NEXT: vmerge.vxm v8, v16, a1, v0
+; CHECK-D-NEXT: fsrm a0
+; CHECK-D-NEXT: ret
;
; CHECK-ZVBB-LABEL: cttz_nxv8i64:
; CHECK-ZVBB: # %bb.0:
@@ -3343,4 +3275,6 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
+; RV32D: {{.*}}
; RV64: {{.*}}
+; RV64D: {{.*}}
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