[llvm] [RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (PR #99251)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 16:00:15 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/99251
A nxvXi64 VMV_V_X_VL on RV32 sign extends its 32 bit input to 64 bits. If that input is positive, the sign extend can also be considered as a zero extend.
>From b0ac7fa8020783bedb5a52563b436ec6d979c729 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 16 Jul 2024 15:53:52 -0700
Subject: [PATCH] [RISCV] Teach fillUpExtensionSupportForSplat to handle
nxvXi64 VMV_V_X_VL on RV32.
A nxvXi64 VMV_V_X_VL on RV32 sign extends its 32 bit input to 64 bits.
If that input is positive, the sign extend can also be considered
as a zero extend.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 18 +-
llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 322 ++++++------------
llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 196 ++++-------
.../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 184 ++++------
.../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 216 ++++--------
.../RISCV/rvv/fixed-vectors-shuffle-rotate.ll | 180 +++++-----
.../CodeGen/RISCV/rvv/fixed-vectors-vrol.ll | 124 ++++---
.../CodeGen/RISCV/rvv/fixed-vectors-vror.ll | 180 ++++++----
.../CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll | 72 ++--
.../CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll | 69 ++--
.../CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll | 19 +-
.../CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll | 78 ++---
llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll | 52 +--
llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll | 52 +--
llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll | 21 +-
llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll | 22 +-
16 files changed, 767 insertions(+), 1038 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 8b5e56bff4097..1e2d25109204a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -14477,10 +14477,22 @@ struct NodeExtensionHelper {
// widening opcode by splatting to smaller element size.
unsigned EltBits = VT.getScalarSizeInBits();
unsigned ScalarBits = Op.getValueSizeInBits();
- // Make sure we're getting all element bits from the scalar register.
- // FIXME: Support implicit sign extension of vmv.v.x?
- if (ScalarBits < EltBits)
+ // Make sure we're not getting all bits from the element, we need special
+ // handling.
+ if (ScalarBits < EltBits) {
+ // This should only occur on RV32.
+ assert(Opc == RISCVISD::VMV_V_X_VL && EltBits == 64 && ScalarBits == 32 &&
+ !Subtarget.is64Bit() && "Unexpected splat");
+ // vmv.v.x sign extends narrow inputs.
+ SupportsSExt = true;
+
+ // If the input is positive, then sign extend is also zero extend.
+ if (DAG.SignBitIsZero(Op))
+ SupportsZExt = true;
+
+ EnforceOneUse = false;
return;
+ }
unsigned NarrowSize = EltBits / 2;
// If the narrow type cannot be expressed with a legal VMV,
diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
index 6e538f3dfb38e..d51f5eacd7d91 100644
--- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
@@ -1229,36 +1229,20 @@ define <vscale x 1 x i64> @ctlz_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_nxv1i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; RV32F-NEXT: vmv.v.x v9, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vwsubu.wv v9, v9, v8
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vminu.vx v8, v9, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_nxv1i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64F-NEXT: vmv.v.x v9, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v10, v8
-; RV64F-NEXT: vsrl.vi v8, v10, 23
-; RV64F-NEXT: vwsubu.vv v10, v9, v8
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV64F-NEXT: vminu.vx v8, v10, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_nxv1i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vmv.v.x v9, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-F-NEXT: vsrl.vi v8, v10, 23
+; CHECK-F-NEXT: vwsubu.vv v10, v9, v8
+; CHECK-F-NEXT: li a1, 64
+; CHECK-F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-F-NEXT: vminu.vx v8, v10, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_nxv1i64:
; CHECK-D: # %bb.0:
@@ -1385,36 +1369,20 @@ define <vscale x 2 x i64> @ctlz_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_nxv2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma
-; RV32F-NEXT: vmv.v.x v10, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v8
-; RV32F-NEXT: vsrl.vi v8, v12, 23
-; RV32F-NEXT: vwsubu.wv v10, v10, v8
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vminu.vx v8, v10, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_nxv2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64F-NEXT: vmv.v.x v10, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v11, v8
-; RV64F-NEXT: vsrl.vi v8, v11, 23
-; RV64F-NEXT: vwsubu.vv v12, v10, v8
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV64F-NEXT: vminu.vx v8, v12, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_nxv2i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vmv.v.x v10, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v11, v8
+; CHECK-F-NEXT: vsrl.vi v8, v11, 23
+; CHECK-F-NEXT: vwsubu.vv v12, v10, v8
+; CHECK-F-NEXT: li a1, 64
+; CHECK-F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-F-NEXT: vminu.vx v8, v12, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_nxv2i64:
; CHECK-D: # %bb.0:
@@ -1541,36 +1509,20 @@ define <vscale x 4 x i64> @ctlz_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_nxv4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma
-; RV32F-NEXT: vmv.v.x v12, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v16, v8
-; RV32F-NEXT: vsrl.vi v8, v16, 23
-; RV32F-NEXT: vwsubu.wv v12, v12, v8
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; RV32F-NEXT: vminu.vx v8, v12, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_nxv4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV64F-NEXT: vmv.v.x v12, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v14, v8
-; RV64F-NEXT: vsrl.vi v8, v14, 23
-; RV64F-NEXT: vwsubu.vv v16, v12, v8
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; RV64F-NEXT: vminu.vx v8, v16, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_nxv4i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vmv.v.x v12, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v14, v8
+; CHECK-F-NEXT: vsrl.vi v8, v14, 23
+; CHECK-F-NEXT: vwsubu.vv v16, v12, v8
+; CHECK-F-NEXT: li a1, 64
+; CHECK-F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-F-NEXT: vminu.vx v8, v16, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_nxv4i64:
; CHECK-D: # %bb.0:
@@ -1697,36 +1649,20 @@ define <vscale x 8 x i64> @ctlz_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_nxv8i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; RV32F-NEXT: vmv.v.x v16, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v24, v8
-; RV32F-NEXT: vsrl.vi v8, v24, 23
-; RV32F-NEXT: vwsubu.wv v16, v16, v8
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32F-NEXT: vminu.vx v8, v16, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_nxv8i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64F-NEXT: vmv.v.x v16, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v20, v8
-; RV64F-NEXT: vsrl.vi v8, v20, 23
-; RV64F-NEXT: vwsubu.vv v24, v16, v8
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV64F-NEXT: vminu.vx v8, v24, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_nxv8i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vmv.v.x v16, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v20, v8
+; CHECK-F-NEXT: vsrl.vi v8, v20, 23
+; CHECK-F-NEXT: vwsubu.vv v24, v16, v8
+; CHECK-F-NEXT: li a1, 64
+; CHECK-F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-F-NEXT: vminu.vx v8, v24, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_nxv8i64:
; CHECK-D: # %bb.0:
@@ -2895,31 +2831,17 @@ define <vscale x 1 x i64> @ctlz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_zero_undef_nxv1i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma
-; RV32F-NEXT: vmv.v.x v9, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vwsubu.wv v9, v9, v8
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: vmv1r.v v8, v9
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_zero_undef_nxv1i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
-; RV64F-NEXT: vmv.v.x v9, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v10, v8
-; RV64F-NEXT: vsrl.vi v10, v10, 23
-; RV64F-NEXT: vwsubu.vv v8, v9, v10
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_zero_undef_nxv1i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vmv.v.x v9, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-F-NEXT: vsrl.vi v10, v10, 23
+; CHECK-F-NEXT: vwsubu.vv v8, v9, v10
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64:
; CHECK-D: # %bb.0:
@@ -3043,31 +2965,17 @@ define <vscale x 2 x i64> @ctlz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_zero_undef_nxv2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma
-; RV32F-NEXT: vmv.v.x v10, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v8
-; RV32F-NEXT: vsrl.vi v8, v12, 23
-; RV32F-NEXT: vwsubu.wv v10, v10, v8
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: vmv2r.v v8, v10
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_zero_undef_nxv2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
-; RV64F-NEXT: vmv.v.x v10, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v11, v8
-; RV64F-NEXT: vsrl.vi v11, v11, 23
-; RV64F-NEXT: vwsubu.vv v8, v10, v11
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_zero_undef_nxv2i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vmv.v.x v10, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v11, v8
+; CHECK-F-NEXT: vsrl.vi v11, v11, 23
+; CHECK-F-NEXT: vwsubu.vv v8, v10, v11
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64:
; CHECK-D: # %bb.0:
@@ -3191,31 +3099,17 @@ define <vscale x 4 x i64> @ctlz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_zero_undef_nxv4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma
-; RV32F-NEXT: vmv.v.x v12, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v16, v8
-; RV32F-NEXT: vsrl.vi v8, v16, 23
-; RV32F-NEXT: vwsubu.wv v12, v12, v8
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: vmv4r.v v8, v12
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_zero_undef_nxv4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
-; RV64F-NEXT: vmv.v.x v12, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v14, v8
-; RV64F-NEXT: vsrl.vi v14, v14, 23
-; RV64F-NEXT: vwsubu.vv v8, v12, v14
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_zero_undef_nxv4i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vmv.v.x v12, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v14, v8
+; CHECK-F-NEXT: vsrl.vi v14, v14, 23
+; CHECK-F-NEXT: vwsubu.vv v8, v12, v14
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64:
; CHECK-D: # %bb.0:
@@ -3339,31 +3233,17 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_zero_undef_nxv8i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: li a0, 190
-; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; RV32F-NEXT: vmv.v.x v16, a0
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v24, v8
-; RV32F-NEXT: vsrl.vi v8, v24, 23
-; RV32F-NEXT: vwsubu.wv v16, v16, v8
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: vmv8r.v v8, v16
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_zero_undef_nxv8i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: li a0, 190
-; RV64F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64F-NEXT: vmv.v.x v16, a0
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vfncvt.f.xu.w v20, v8
-; RV64F-NEXT: vsrl.vi v20, v20, 23
-; RV64F-NEXT: vwsubu.vv v8, v16, v20
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: ctlz_zero_undef_nxv8i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: li a0, 190
+; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vmv.v.x v16, a0
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vfncvt.f.xu.w v20, v8
+; CHECK-F-NEXT: vsrl.vi v20, v20, 23
+; CHECK-F-NEXT: vwsubu.vv v8, v16, v20
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64:
; CHECK-D: # %bb.0:
@@ -3387,4 +3267,6 @@ define <vscale x 8 x i64> @ctlz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32: {{.*}}
+; RV32F: {{.*}}
; RV64: {{.*}}
+; RV64F: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
index 479664c6f5f62..9737107974075 100644
--- a/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
@@ -1223,12 +1223,11 @@ define <vscale x 1 x i64> @cttz_nxv1i64(<vscale x 1 x i64> %va) {
; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v9, v8
; RV32F-NEXT: vsrl.vi v8, v9, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vzext.vf2 v9, v8
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v9, a1
+; RV32F-NEXT: vwsubu.vx v9, v8, a1
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32F-NEXT: vmerge.vxm v8, v9, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1385,12 +1384,11 @@ define <vscale x 2 x i64> @cttz_nxv2i64(<vscale x 2 x i64> %va) {
; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v10, v8
; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vzext.vf2 v10, v8
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v10, a1
+; RV32F-NEXT: vwsubu.vx v10, v8, a1
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32F-NEXT: vmerge.vxm v8, v10, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1547,12 +1545,11 @@ define <vscale x 4 x i64> @cttz_nxv4i64(<vscale x 4 x i64> %va) {
; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v12, v8
; RV32F-NEXT: vsrl.vi v8, v12, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; RV32F-NEXT: vzext.vf2 v12, v8
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v12, a1
+; RV32F-NEXT: vwsubu.vx v12, v8, a1
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32F-NEXT: vmerge.vxm v8, v12, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -1709,12 +1706,11 @@ define <vscale x 8 x i64> @cttz_nxv8i64(<vscale x 8 x i64> %va) {
; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; RV32F-NEXT: vfncvt.f.xu.w v16, v8
; RV32F-NEXT: vsrl.vi v8, v16, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32F-NEXT: vzext.vf2 v16, v8
; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v16, a1
+; RV32F-NEXT: vwsubu.vx v16, v8, a1
; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v8, a1, v0
+; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; RV32F-NEXT: vmerge.vxm v8, v16, a1, v0
; RV32F-NEXT: fsrm a0
; RV32F-NEXT: ret
;
@@ -2887,35 +2883,19 @@ define <vscale x 1 x i64> @cttz_zero_undef_nxv1i64(<vscale x 1 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_zero_undef_nxv1i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV32F-NEXT: vrsub.vi v9, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v9
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v9, v8
-; RV32F-NEXT: vsrl.vi v8, v9, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vzext.vf2 v9, v8
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v9, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_zero_undef_nxv1i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
-; RV64F-NEXT: vrsub.vi v9, v8, 0
-; RV64F-NEXT: vand.vv v8, v8, v9
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v9, v8
-; RV64F-NEXT: vsrl.vi v9, v9, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v8, v9, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: cttz_zero_undef_nxv1i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: vsetvli a0, zero, e64, m1, ta, ma
+; CHECK-F-NEXT: vrsub.vi v9, v8, 0
+; CHECK-F-NEXT: vand.vv v8, v8, v9
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v9, v8
+; CHECK-F-NEXT: vsrl.vi v9, v9, 23
+; CHECK-F-NEXT: li a1, 127
+; CHECK-F-NEXT: vwsubu.vx v8, v9, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_zero_undef_nxv1i64:
; CHECK-D: # %bb.0:
@@ -3021,35 +3001,19 @@ define <vscale x 2 x i64> @cttz_zero_undef_nxv2i64(<vscale x 2 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_zero_undef_nxv2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; RV32F-NEXT: vrsub.vi v10, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v10
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vzext.vf2 v10, v8
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v10, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_zero_undef_nxv2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; RV64F-NEXT: vrsub.vi v10, v8, 0
-; RV64F-NEXT: vand.vv v8, v8, v10
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v10, v8
-; RV64F-NEXT: vsrl.vi v10, v10, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v8, v10, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: cttz_zero_undef_nxv2i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: vsetvli a0, zero, e64, m2, ta, ma
+; CHECK-F-NEXT: vrsub.vi v10, v8, 0
+; CHECK-F-NEXT: vand.vv v8, v8, v10
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v10, v8
+; CHECK-F-NEXT: vsrl.vi v10, v10, 23
+; CHECK-F-NEXT: li a1, 127
+; CHECK-F-NEXT: vwsubu.vx v8, v10, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_zero_undef_nxv2i64:
; CHECK-D: # %bb.0:
@@ -3155,35 +3119,19 @@ define <vscale x 4 x i64> @cttz_zero_undef_nxv4i64(<vscale x 4 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_zero_undef_nxv4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV32F-NEXT: vrsub.vi v12, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v12
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v8
-; RV32F-NEXT: vsrl.vi v8, v12, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma
-; RV32F-NEXT: vzext.vf2 v12, v8
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v12, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_zero_undef_nxv4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
-; RV64F-NEXT: vrsub.vi v12, v8, 0
-; RV64F-NEXT: vand.vv v8, v8, v12
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v12, v8
-; RV64F-NEXT: vsrl.vi v12, v12, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v8, v12, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: cttz_zero_undef_nxv4i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: vsetvli a0, zero, e64, m4, ta, ma
+; CHECK-F-NEXT: vrsub.vi v12, v8, 0
+; CHECK-F-NEXT: vand.vv v8, v8, v12
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v12, v8
+; CHECK-F-NEXT: vsrl.vi v12, v12, 23
+; CHECK-F-NEXT: li a1, 127
+; CHECK-F-NEXT: vwsubu.vx v8, v12, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_zero_undef_nxv4i64:
; CHECK-D: # %bb.0:
@@ -3289,35 +3237,19 @@ define <vscale x 8 x i64> @cttz_zero_undef_nxv8i64(<vscale x 8 x i64> %va) {
; RV64I-NEXT: vsrl.vx v8, v8, a0
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_zero_undef_nxv8i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV32F-NEXT: vrsub.vi v16, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v16
-; RV32F-NEXT: fsrmi a0, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v16, v8
-; RV32F-NEXT: vsrl.vi v8, v16, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma
-; RV32F-NEXT: vzext.vf2 v16, v8
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v16, a1
-; RV32F-NEXT: fsrm a0
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_zero_undef_nxv8i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
-; RV64F-NEXT: vrsub.vi v16, v8, 0
-; RV64F-NEXT: vand.vv v8, v8, v16
-; RV64F-NEXT: fsrmi a0, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v16, v8
-; RV64F-NEXT: vsrl.vi v16, v16, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v8, v16, a1
-; RV64F-NEXT: fsrm a0
-; RV64F-NEXT: ret
+; CHECK-F-LABEL: cttz_zero_undef_nxv8i64:
+; CHECK-F: # %bb.0:
+; CHECK-F-NEXT: vsetvli a0, zero, e64, m8, ta, ma
+; CHECK-F-NEXT: vrsub.vi v16, v8, 0
+; CHECK-F-NEXT: vand.vv v8, v8, v16
+; CHECK-F-NEXT: fsrmi a0, 1
+; CHECK-F-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-F-NEXT: vfncvt.f.xu.w v16, v8
+; CHECK-F-NEXT: vsrl.vi v16, v16, 23
+; CHECK-F-NEXT: li a1, 127
+; CHECK-F-NEXT: vwsubu.vx v8, v16, a1
+; CHECK-F-NEXT: fsrm a0
+; CHECK-F-NEXT: ret
;
; CHECK-D-LABEL: cttz_zero_undef_nxv8i64:
; CHECK-D: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
index 49e5a1c79c43b..228a9f0d6d522 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
@@ -347,40 +347,22 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_v2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: li a1, 190
-; RV32F-NEXT: vmv.v.x v9, a1
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vwsubu.wv v9, v9, v8
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vminu.vx v8, v9, a1
-; RV32F-NEXT: vse64.v v8, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_v2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: li a1, 190
-; RV64F-NEXT: vmv.v.x v9, a1
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vfncvt.f.xu.w v10, v8
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v8, v10, 23
-; RV64F-NEXT: vwsubu.vv v10, v9, v8
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV64F-NEXT: vminu.vx v8, v10, a1
-; RV64F-NEXT: vse64.v v8, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: ctlz_v2i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: li a1, 190
+; RVF-NEXT: vmv.v.x v9, a1
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vfncvt.f.xu.w v10, v8
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v8, v10, 23
+; RVF-NEXT: vwsubu.vv v10, v9, v8
+; RVF-NEXT: li a1, 64
+; RVF-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RVF-NEXT: vminu.vx v8, v10, a1
+; RVF-NEXT: vse64.v v8, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: ctlz_v2i64:
; RVD: # %bb.0:
@@ -756,40 +738,22 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_v4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: li a1, 190
-; RV32F-NEXT: vmv.v.x v10, a1
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v8
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v8, v12, 23
-; RV32F-NEXT: vwsubu.wv v10, v10, v8
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vminu.vx v8, v10, a1
-; RV32F-NEXT: vse64.v v8, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_v4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: li a1, 190
-; RV64F-NEXT: vmv.v.x v10, a1
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vfncvt.f.xu.w v11, v8
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v8, v11, 23
-; RV64F-NEXT: vwsubu.vv v12, v10, v8
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV64F-NEXT: vminu.vx v8, v12, a1
-; RV64F-NEXT: vse64.v v8, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: ctlz_v4i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: li a1, 190
+; RVF-NEXT: vmv.v.x v10, a1
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vfncvt.f.xu.w v11, v8
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v8, v11, 23
+; RVF-NEXT: vwsubu.vv v12, v10, v8
+; RVF-NEXT: li a1, 64
+; RVF-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RVF-NEXT: vminu.vx v8, v12, a1
+; RVF-NEXT: vse64.v v8, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: ctlz_v4i64:
; RVD: # %bb.0:
@@ -1146,34 +1110,19 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_zero_undef_v2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: li a1, 190
-; RV32F-NEXT: vmv.v.x v9, a1
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vwsubu.wv v9, v9, v8
-; RV32F-NEXT: vse64.v v9, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_zero_undef_v2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: li a1, 190
-; RV64F-NEXT: vmv.v.x v9, a1
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vfncvt.f.xu.w v10, v8
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v8, v10, 23
-; RV64F-NEXT: vwsubu.vv v10, v9, v8
-; RV64F-NEXT: vse64.v v10, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: ctlz_zero_undef_v2i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: li a1, 190
+; RVF-NEXT: vmv.v.x v9, a1
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vfncvt.f.xu.w v10, v8
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v8, v10, 23
+; RVF-NEXT: vwsubu.vv v10, v9, v8
+; RVF-NEXT: vse64.v v10, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: ctlz_zero_undef_v2i64:
; RVD: # %bb.0:
@@ -1531,34 +1480,19 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: ctlz_zero_undef_v4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: li a1, 190
-; RV32F-NEXT: vmv.v.x v10, a1
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v8
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v8, v12, 23
-; RV32F-NEXT: vwsubu.wv v10, v10, v8
-; RV32F-NEXT: vse64.v v10, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: ctlz_zero_undef_v4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: li a1, 190
-; RV64F-NEXT: vmv.v.x v10, a1
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vfncvt.f.xu.w v11, v8
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v8, v11, 23
-; RV64F-NEXT: vwsubu.vv v12, v10, v8
-; RV64F-NEXT: vse64.v v12, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: ctlz_zero_undef_v4i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: li a1, 190
+; RVF-NEXT: vmv.v.x v10, a1
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vfncvt.f.xu.w v11, v8
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v8, v11, 23
+; RVF-NEXT: vwsubu.vv v12, v10, v8
+; RVF-NEXT: vse64.v v12, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: ctlz_zero_undef_v4i64:
; RVD: # %bb.0:
@@ -1589,4 +1523,6 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32D: {{.*}}
+; RV32F: {{.*}}
; RV64D: {{.*}}
+; RV64F: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
index ea3a78ae0becc..4b1691aada5be 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
@@ -330,46 +330,25 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_v2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: vrsub.vi v9, v8, 0
-; RV32F-NEXT: vand.vv v9, v8, v9
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v9
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v9, v10, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vzext.vf2 v10, v9
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v9, v10, a1
-; RV32F-NEXT: vmseq.vi v0, v8, 0
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v9, a1, v0
-; RV32F-NEXT: vse64.v v8, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_v2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: vrsub.vi v9, v8, 0
-; RV64F-NEXT: vand.vv v9, v8, v9
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v10, v9
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v9, v10, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v10, v9, a1
-; RV64F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV64F-NEXT: vmseq.vi v0, v8, 0
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vmerge.vxm v8, v10, a1, v0
-; RV64F-NEXT: vse64.v v8, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: cttz_v2i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: vrsub.vi v9, v8, 0
+; RVF-NEXT: vand.vv v9, v8, v9
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RVF-NEXT: vfncvt.f.xu.w v10, v9
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v9, v10, 23
+; RVF-NEXT: li a1, 127
+; RVF-NEXT: vwsubu.vx v10, v9, a1
+; RVF-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RVF-NEXT: vmseq.vi v0, v8, 0
+; RVF-NEXT: li a1, 64
+; RVF-NEXT: vmerge.vxm v8, v10, a1, v0
+; RVF-NEXT: vse64.v v8, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: cttz_v2i64:
; RVD: # %bb.0:
@@ -731,46 +710,25 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_v4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: vrsub.vi v10, v8, 0
-; RV32F-NEXT: vand.vv v10, v8, v10
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v12, v10
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v10, v12, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vzext.vf2 v12, v10
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v10, v12, a1
-; RV32F-NEXT: vmseq.vi v0, v8, 0
-; RV32F-NEXT: li a1, 64
-; RV32F-NEXT: vmerge.vxm v8, v10, a1, v0
-; RV32F-NEXT: vse64.v v8, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_v4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: vrsub.vi v10, v8, 0
-; RV64F-NEXT: vand.vv v10, v8, v10
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v12, v10
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v10, v12, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v12, v10, a1
-; RV64F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV64F-NEXT: vmseq.vi v0, v8, 0
-; RV64F-NEXT: li a1, 64
-; RV64F-NEXT: vmerge.vxm v8, v12, a1, v0
-; RV64F-NEXT: vse64.v v8, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: cttz_v4i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: vrsub.vi v10, v8, 0
+; RVF-NEXT: vand.vv v10, v8, v10
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RVF-NEXT: vfncvt.f.xu.w v12, v10
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v10, v12, 23
+; RVF-NEXT: li a1, 127
+; RVF-NEXT: vwsubu.vx v12, v10, a1
+; RVF-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RVF-NEXT: vmseq.vi v0, v8, 0
+; RVF-NEXT: li a1, 64
+; RVF-NEXT: vmerge.vxm v8, v12, a1, v0
+; RVF-NEXT: vse64.v v8, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: cttz_v4i64:
; RVD: # %bb.0:
@@ -1109,39 +1067,21 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_zero_undef_v2i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: vrsub.vi v9, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v9
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v9, v8
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v8, v9, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma
-; RV32F-NEXT: vzext.vf2 v9, v8
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v9, a1
-; RV32F-NEXT: vse64.v v8, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_zero_undef_v2i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: vrsub.vi v9, v8, 0
-; RV64F-NEXT: vand.vv v8, v8, v9
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v9, v8
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v8, v9, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v9, v8, a1
-; RV64F-NEXT: vse64.v v9, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: cttz_zero_undef_v2i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: vrsub.vi v9, v8, 0
+; RVF-NEXT: vand.vv v8, v8, v9
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RVF-NEXT: vfncvt.f.xu.w v9, v8
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v8, v9, 23
+; RVF-NEXT: li a1, 127
+; RVF-NEXT: vwsubu.vx v9, v8, a1
+; RVF-NEXT: vse64.v v9, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: cttz_zero_undef_v2i64:
; RVD: # %bb.0:
@@ -1480,39 +1420,21 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
; RV64I-NEXT: vse64.v v8, (a0)
; RV64I-NEXT: ret
;
-; RV32F-LABEL: cttz_zero_undef_v4i64:
-; RV32F: # %bb.0:
-; RV32F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32F-NEXT: vle64.v v8, (a0)
-; RV32F-NEXT: vrsub.vi v10, v8, 0
-; RV32F-NEXT: vand.vv v8, v8, v10
-; RV32F-NEXT: fsrmi a1, 1
-; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV32F-NEXT: vfncvt.f.xu.w v10, v8
-; RV32F-NEXT: fsrm a1
-; RV32F-NEXT: vsrl.vi v8, v10, 23
-; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma
-; RV32F-NEXT: vzext.vf2 v10, v8
-; RV32F-NEXT: li a1, 127
-; RV32F-NEXT: vsub.vx v8, v10, a1
-; RV32F-NEXT: vse64.v v8, (a0)
-; RV32F-NEXT: ret
-;
-; RV64F-LABEL: cttz_zero_undef_v4i64:
-; RV64F: # %bb.0:
-; RV64F-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV64F-NEXT: vle64.v v8, (a0)
-; RV64F-NEXT: vrsub.vi v10, v8, 0
-; RV64F-NEXT: vand.vv v8, v8, v10
-; RV64F-NEXT: fsrmi a1, 1
-; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma
-; RV64F-NEXT: vfncvt.f.xu.w v10, v8
-; RV64F-NEXT: fsrm a1
-; RV64F-NEXT: vsrl.vi v8, v10, 23
-; RV64F-NEXT: li a1, 127
-; RV64F-NEXT: vwsubu.vx v10, v8, a1
-; RV64F-NEXT: vse64.v v10, (a0)
-; RV64F-NEXT: ret
+; RVF-LABEL: cttz_zero_undef_v4i64:
+; RVF: # %bb.0:
+; RVF-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RVF-NEXT: vle64.v v8, (a0)
+; RVF-NEXT: vrsub.vi v10, v8, 0
+; RVF-NEXT: vand.vv v8, v8, v10
+; RVF-NEXT: fsrmi a1, 1
+; RVF-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RVF-NEXT: vfncvt.f.xu.w v10, v8
+; RVF-NEXT: fsrm a1
+; RVF-NEXT: vsrl.vi v8, v10, 23
+; RVF-NEXT: li a1, 127
+; RVF-NEXT: vwsubu.vx v10, v8, a1
+; RVF-NEXT: vse64.v v10, (a0)
+; RVF-NEXT: ret
;
; RVD-LABEL: cttz_zero_undef_v4i64:
; RVD: # %bb.0:
@@ -1545,4 +1467,6 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind {
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; RV32D: {{.*}}
+; RV32F: {{.*}}
; RV64D: {{.*}}
+; RV64F: {{.*}}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
index 4c84cf350c40e..17a63eff26ac1 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
@@ -479,16 +479,18 @@ define <8 x i16> @shuffle_v8i16_as_i32(<8 x i16> %v) {
define <8 x i16> @shuffle_v8i16_as_i64_16(<8 x i16> %v) {
; RV32-LABEL: shuffle_v8i16_as_i64_16:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a0, 48
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v10, v9, a0
-; RV32-NEXT: vsll.vv v10, v8, v10
-; RV32-NEXT: vrsub.vi v9, v9, 0
-; RV32-NEXT: vand.vx v9, v9, a0
-; RV32-NEXT: vsrl.vv v8, v8, v9
-; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vwsubu.vx v10, v9, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v9, v10, a1
+; RV32-NEXT: vsrl.vv v9, v8, v9
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vand.vx v10, v10, a1
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8i16_as_i64_16:
@@ -523,16 +525,18 @@ define <8 x i16> @shuffle_v8i16_as_i64_16(<8 x i16> %v) {
define <8 x i16> @shuffle_v8i16_as_i64_32(<8 x i16> %v) {
; RV32-LABEL: shuffle_v8i16_as_i64_32:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a0, 32
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v10, v9, a0
-; RV32-NEXT: vsll.vv v10, v8, v10
-; RV32-NEXT: vrsub.vi v9, v9, 0
-; RV32-NEXT: vand.vx v9, v9, a0
-; RV32-NEXT: vsrl.vv v8, v8, v9
-; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vwsubu.vx v10, v9, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v9, v10, a1
+; RV32-NEXT: vsrl.vv v9, v8, v9
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vand.vx v10, v10, a1
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8i16_as_i64_32:
@@ -567,16 +571,18 @@ define <8 x i16> @shuffle_v8i16_as_i64_32(<8 x i16> %v) {
define <8 x i16> @shuffle_v8i16_as_i64_48(<8 x i16> %v) {
; RV32-LABEL: shuffle_v8i16_as_i64_48:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a0, 16
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v10, v9, a0
-; RV32-NEXT: vsll.vv v10, v8, v10
-; RV32-NEXT: vrsub.vi v9, v9, 0
-; RV32-NEXT: vand.vx v9, v9, a0
-; RV32-NEXT: vsrl.vv v8, v8, v9
-; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vwsubu.vx v10, v9, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v9, v10, a1
+; RV32-NEXT: vsrl.vv v9, v8, v9
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vand.vx v10, v10, a1
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8i16_as_i64_48:
@@ -611,16 +617,18 @@ define <8 x i16> @shuffle_v8i16_as_i64_48(<8 x i16> %v) {
define <8 x i32> @shuffle_v8i32_as_i64(<8 x i32> %v) {
; RV32-LABEL: shuffle_v8i32_as_i64:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: li a0, 32
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v12, v10, a0
-; RV32-NEXT: vsll.vv v12, v8, v12
-; RV32-NEXT: vrsub.vi v10, v10, 0
-; RV32-NEXT: vand.vx v10, v10, a0
-; RV32-NEXT: vsrl.vv v8, v8, v10
-; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vwsubu.vx v12, v10, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vand.vx v10, v12, a1
+; RV32-NEXT: vsrl.vv v10, v8, v10
+; RV32-NEXT: vmv.v.x v12, a0
+; RV32-NEXT: vand.vx v12, v12, a1
+; RV32-NEXT: vsll.vv v8, v8, v12
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8i32_as_i64:
@@ -680,16 +688,18 @@ define <8 x half> @shuffle_v8f16_as_i32(<8 x half> %v) {
define <8 x half> @shuffle_v8f16_as_i64_16(<8 x half> %v) {
; RV32-LABEL: shuffle_v8f16_as_i64_16:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a0, 48
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v10, v9, a0
-; RV32-NEXT: vsll.vv v10, v8, v10
-; RV32-NEXT: vrsub.vi v9, v9, 0
-; RV32-NEXT: vand.vx v9, v9, a0
-; RV32-NEXT: vsrl.vv v8, v8, v9
-; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vwsubu.vx v10, v9, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v9, v10, a1
+; RV32-NEXT: vsrl.vv v9, v8, v9
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vand.vx v10, v10, a1
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8f16_as_i64_16:
@@ -724,16 +734,18 @@ define <8 x half> @shuffle_v8f16_as_i64_16(<8 x half> %v) {
define <8 x half> @shuffle_v8f16_as_i64_32(<8 x half> %v) {
; RV32-LABEL: shuffle_v8f16_as_i64_32:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a0, 32
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v10, v9, a0
-; RV32-NEXT: vsll.vv v10, v8, v10
-; RV32-NEXT: vrsub.vi v9, v9, 0
-; RV32-NEXT: vand.vx v9, v9, a0
-; RV32-NEXT: vsrl.vv v8, v8, v9
-; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vwsubu.vx v10, v9, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v9, v10, a1
+; RV32-NEXT: vsrl.vv v9, v8, v9
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vand.vx v10, v10, a1
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8f16_as_i64_32:
@@ -768,16 +780,18 @@ define <8 x half> @shuffle_v8f16_as_i64_32(<8 x half> %v) {
define <8 x half> @shuffle_v8f16_as_i64_48(<8 x half> %v) {
; RV32-LABEL: shuffle_v8f16_as_i64_48:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v9, 0
; RV32-NEXT: li a0, 16
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vmv.v.x v9, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v10, v9, a0
-; RV32-NEXT: vsll.vv v10, v8, v10
-; RV32-NEXT: vrsub.vi v9, v9, 0
-; RV32-NEXT: vand.vx v9, v9, a0
-; RV32-NEXT: vsrl.vv v8, v8, v9
-; RV32-NEXT: vor.vv v8, v10, v8
+; RV32-NEXT: vwsubu.vx v10, v9, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v9, v10, a1
+; RV32-NEXT: vsrl.vv v9, v8, v9
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vand.vx v10, v10, a1
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8f16_as_i64_48:
@@ -812,16 +826,18 @@ define <8 x half> @shuffle_v8f16_as_i64_48(<8 x half> %v) {
define <8 x float> @shuffle_v8f32_as_i64(<8 x float> %v) {
; RV32-LABEL: shuffle_v8f32_as_i64:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: li a0, 32
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v12, v10, a0
-; RV32-NEXT: vsll.vv v12, v8, v12
-; RV32-NEXT: vrsub.vi v10, v10, 0
-; RV32-NEXT: vand.vx v10, v10, a0
-; RV32-NEXT: vsrl.vv v8, v8, v10
-; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vwsubu.vx v12, v10, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vand.vx v10, v12, a1
+; RV32-NEXT: vsrl.vv v10, v8, v10
+; RV32-NEXT: vmv.v.x v12, a0
+; RV32-NEXT: vand.vx v12, v12, a1
+; RV32-NEXT: vsll.vv v8, v8, v12
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8f32_as_i64:
@@ -857,16 +873,18 @@ define <8 x float> @shuffle_v8f32_as_i64(<8 x float> %v) {
define <8 x float> @shuffle_v8f32_as_i64_exact(<8 x float> %v) vscale_range(2,2) {
; RV32-LABEL: shuffle_v8f32_as_i64_exact:
; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.i v10, 0
; RV32-NEXT: li a0, 32
-; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; RV32-NEXT: vmv.v.x v10, a0
-; RV32-NEXT: li a0, 63
-; RV32-NEXT: vand.vx v12, v10, a0
-; RV32-NEXT: vsll.vv v12, v8, v12
-; RV32-NEXT: vrsub.vi v10, v10, 0
-; RV32-NEXT: vand.vx v10, v10, a0
-; RV32-NEXT: vsrl.vv v8, v8, v10
-; RV32-NEXT: vor.vv v8, v12, v8
+; RV32-NEXT: vwsubu.vx v12, v10, a0
+; RV32-NEXT: li a1, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vand.vx v10, v12, a1
+; RV32-NEXT: vsrl.vv v10, v8, v10
+; RV32-NEXT: vmv.v.x v12, a0
+; RV32-NEXT: vand.vx v12, v12, a1
+; RV32-NEXT: vsll.vv v8, v8, v12
+; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret
;
; RV64-LABEL: shuffle_v8f32_as_i64_exact:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
index e719c6f374973..418b159c8fb98 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrol.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
; RUN: llc -mtriple=riscv32 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
; RUN: llc -mtriple=riscv64 -mattr=+v,+zvkb -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK-ZVKB
@@ -946,18 +946,34 @@ define <2 x i64> @vrol_vv_v2i64(<2 x i64> %a, <2 x i64> %b) {
}
define <2 x i64> @vrol_vx_v2i64(<2 x i64> %a, i64 %b) {
-; CHECK-LABEL: vrol_vx_v2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: vsll.vv v10, v8, v10
-; CHECK-NEXT: vrsub.vi v9, v9, 0
-; CHECK-NEXT: vand.vx v9, v9, a0
-; CHECK-NEXT: vsrl.vv v8, v8, v9
-; CHECK-NEXT: vor.vv v8, v10, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vrol_vx_v2i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV32-NEXT: vmv.v.x v9, a0
+; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; RV32-NEXT: vmv.v.i v10, 0
+; RV32-NEXT: vwsub.vx v11, v10, a0
+; RV32-NEXT: li a0, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; RV32-NEXT: vand.vx v10, v11, a0
+; RV32-NEXT: vsrl.vv v10, v8, v10
+; RV32-NEXT: vand.vx v9, v9, a0
+; RV32-NEXT: vsll.vv v8, v8, v9
+; RV32-NEXT: vor.vv v8, v8, v10
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vrol_vx_v2i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; RV64-NEXT: vmv.v.x v9, a0
+; RV64-NEXT: li a0, 63
+; RV64-NEXT: vand.vx v10, v9, a0
+; RV64-NEXT: vsll.vv v10, v8, v10
+; RV64-NEXT: vrsub.vi v9, v9, 0
+; RV64-NEXT: vand.vx v9, v9, a0
+; RV64-NEXT: vsrl.vv v8, v8, v9
+; RV64-NEXT: vor.vv v8, v10, v8
+; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vrol_vx_v2i64:
; CHECK-ZVKB: # %bb.0:
@@ -995,18 +1011,34 @@ define <4 x i64> @vrol_vv_v4i64(<4 x i64> %a, <4 x i64> %b) {
}
define <4 x i64> @vrol_vx_v4i64(<4 x i64> %a, i64 %b) {
-; CHECK-LABEL: vrol_vx_v4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v12, v10, a0
-; CHECK-NEXT: vsll.vv v12, v8, v12
-; CHECK-NEXT: vrsub.vi v10, v10, 0
-; CHECK-NEXT: vand.vx v10, v10, a0
-; CHECK-NEXT: vsrl.vv v8, v8, v10
-; CHECK-NEXT: vor.vv v8, v12, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vrol_vx_v4i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV32-NEXT: vmv.v.x v10, a0
+; RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; RV32-NEXT: vmv.v.i v12, 0
+; RV32-NEXT: vwsub.vx v14, v12, a0
+; RV32-NEXT: li a0, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; RV32-NEXT: vand.vx v12, v14, a0
+; RV32-NEXT: vsrl.vv v12, v8, v12
+; RV32-NEXT: vand.vx v10, v10, a0
+; RV32-NEXT: vsll.vv v8, v8, v10
+; RV32-NEXT: vor.vv v8, v8, v12
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vrol_vx_v4i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; RV64-NEXT: vmv.v.x v10, a0
+; RV64-NEXT: li a0, 63
+; RV64-NEXT: vand.vx v12, v10, a0
+; RV64-NEXT: vsll.vv v12, v8, v12
+; RV64-NEXT: vrsub.vi v10, v10, 0
+; RV64-NEXT: vand.vx v10, v10, a0
+; RV64-NEXT: vsrl.vv v8, v8, v10
+; RV64-NEXT: vor.vv v8, v12, v8
+; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vrol_vx_v4i64:
; CHECK-ZVKB: # %bb.0:
@@ -1044,18 +1076,34 @@ define <8 x i64> @vrol_vv_v8i64(<8 x i64> %a, <8 x i64> %b) {
}
define <8 x i64> @vrol_vx_v8i64(<8 x i64> %a, i64 %b) {
-; CHECK-LABEL: vrol_vx_v8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v16, v12, a0
-; CHECK-NEXT: vsll.vv v16, v8, v16
-; CHECK-NEXT: vrsub.vi v12, v12, 0
-; CHECK-NEXT: vand.vx v12, v12, a0
-; CHECK-NEXT: vsrl.vv v8, v8, v12
-; CHECK-NEXT: vor.vv v8, v16, v8
-; CHECK-NEXT: ret
+; RV32-LABEL: vrol_vx_v8i64:
+; RV32: # %bb.0:
+; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV32-NEXT: vmv.v.x v12, a0
+; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; RV32-NEXT: vmv.v.i v16, 0
+; RV32-NEXT: vwsub.vx v20, v16, a0
+; RV32-NEXT: li a0, 63
+; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; RV32-NEXT: vand.vx v16, v20, a0
+; RV32-NEXT: vsrl.vv v16, v8, v16
+; RV32-NEXT: vand.vx v12, v12, a0
+; RV32-NEXT: vsll.vv v8, v8, v12
+; RV32-NEXT: vor.vv v8, v8, v16
+; RV32-NEXT: ret
+;
+; RV64-LABEL: vrol_vx_v8i64:
+; RV64: # %bb.0:
+; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; RV64-NEXT: vmv.v.x v12, a0
+; RV64-NEXT: li a0, 63
+; RV64-NEXT: vand.vx v16, v12, a0
+; RV64-NEXT: vsll.vv v16, v8, v16
+; RV64-NEXT: vrsub.vi v12, v12, 0
+; RV64-NEXT: vand.vx v12, v12, a0
+; RV64-NEXT: vsrl.vv v8, v8, v12
+; RV64-NEXT: vor.vv v8, v16, v8
+; RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vrol_vx_v8i64:
; CHECK-ZVKB: # %bb.0:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
index 367c56caf813d..e4ddfeb4c4195 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vror.ll
@@ -1692,18 +1692,34 @@ define <2 x i64> @vror_vv_v2i64(<2 x i64> %a, <2 x i64> %b) {
}
define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) {
-; CHECK-LABEL: vror_vx_v2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v10, v9, a0
-; CHECK-NEXT: vsrl.vv v10, v8, v10
-; CHECK-NEXT: vrsub.vi v9, v9, 0
-; CHECK-NEXT: vand.vx v9, v9, a0
-; CHECK-NEXT: vsll.vv v8, v8, v9
-; CHECK-NEXT: vor.vv v8, v10, v8
-; CHECK-NEXT: ret
+; CHECK-RV32-LABEL: vror_vx_v2i64:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.x v9, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v10, 0
+; CHECK-RV32-NEXT: vwsub.vx v11, v10, a0
+; CHECK-RV32-NEXT: li a0, 63
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vand.vx v10, v11, a0
+; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
+; CHECK-RV32-NEXT: vand.vx v9, v9, a0
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
+; CHECK-RV32-NEXT: vor.vv v8, v8, v10
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vror_vx_v2i64:
+; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
+; CHECK-RV64-NEXT: vmv.v.x v9, a0
+; CHECK-RV64-NEXT: li a0, 63
+; CHECK-RV64-NEXT: vand.vx v10, v9, a0
+; CHECK-RV64-NEXT: vsrl.vv v10, v8, v10
+; CHECK-RV64-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV64-NEXT: vand.vx v9, v9, a0
+; CHECK-RV64-NEXT: vsll.vv v8, v8, v9
+; CHECK-RV64-NEXT: vor.vv v8, v10, v8
+; CHECK-RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vror_vx_v2i64:
; CHECK-ZVKB: # %bb.0:
@@ -1719,11 +1735,13 @@ define <2 x i64> @vror_vx_v2i64(<2 x i64> %a, i64 %b) {
define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v2i64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.v.i v9, 1
-; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v9, 0
+; CHECK-RV32-NEXT: li a0, 1
+; CHECK-RV32-NEXT: vwsubu.vx v10, v9, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v9, v9, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vand.vx v9, v10, a0
; CHECK-RV32-NEXT: vsll.vv v9, v8, v9
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
@@ -1752,11 +1770,13 @@ define <2 x i64> @vror_vi_v2i64(<2 x i64> %a) {
define <2 x i64> @vror_vi_rotl_v2i64(<2 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_v2i64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; CHECK-RV32-NEXT: vmv.v.i v9, 1
-; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v9, 0
+; CHECK-RV32-NEXT: li a0, 1
+; CHECK-RV32-NEXT: vwsubu.vx v10, v9, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v9, v9, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vand.vx v9, v10, a0
; CHECK-RV32-NEXT: vsrl.vv v9, v8, v9
; CHECK-RV32-NEXT: vmv.v.x v10, a0
; CHECK-RV32-NEXT: vand.vi v10, v10, 1
@@ -1808,18 +1828,34 @@ define <4 x i64> @vror_vv_v4i64(<4 x i64> %a, <4 x i64> %b) {
}
define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) {
-; CHECK-LABEL: vror_vx_v4i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v12, v10, a0
-; CHECK-NEXT: vsrl.vv v12, v8, v12
-; CHECK-NEXT: vrsub.vi v10, v10, 0
-; CHECK-NEXT: vand.vx v10, v10, a0
-; CHECK-NEXT: vsll.vv v8, v8, v10
-; CHECK-NEXT: vor.vv v8, v12, v8
-; CHECK-NEXT: ret
+; CHECK-RV32-LABEL: vror_vx_v4i64:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.x v10, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v12, 0
+; CHECK-RV32-NEXT: vwsub.vx v14, v12, a0
+; CHECK-RV32-NEXT: li a0, 63
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vand.vx v12, v14, a0
+; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
+; CHECK-RV32-NEXT: vand.vx v10, v10, a0
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
+; CHECK-RV32-NEXT: vor.vv v8, v8, v12
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vror_vx_v4i64:
+; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
+; CHECK-RV64-NEXT: vmv.v.x v10, a0
+; CHECK-RV64-NEXT: li a0, 63
+; CHECK-RV64-NEXT: vand.vx v12, v10, a0
+; CHECK-RV64-NEXT: vsrl.vv v12, v8, v12
+; CHECK-RV64-NEXT: vrsub.vi v10, v10, 0
+; CHECK-RV64-NEXT: vand.vx v10, v10, a0
+; CHECK-RV64-NEXT: vsll.vv v8, v8, v10
+; CHECK-RV64-NEXT: vor.vv v8, v12, v8
+; CHECK-RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vror_vx_v4i64:
; CHECK-ZVKB: # %bb.0:
@@ -1835,11 +1871,13 @@ define <4 x i64> @vror_vx_v4i64(<4 x i64> %a, i64 %b) {
define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v4i64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-RV32-NEXT: vmv.v.i v10, 1
-; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v10, 0
+; CHECK-RV32-NEXT: li a0, 1
+; CHECK-RV32-NEXT: vwsubu.vx v12, v10, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v10, v10, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vand.vx v10, v12, a0
; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
@@ -1868,11 +1906,13 @@ define <4 x i64> @vror_vi_v4i64(<4 x i64> %a) {
define <4 x i64> @vror_vi_rotl_v4i64(<4 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_v4i64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-RV32-NEXT: vmv.v.i v10, 1
-; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v10, 0
+; CHECK-RV32-NEXT: li a0, 1
+; CHECK-RV32-NEXT: vwsubu.vx v12, v10, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v10, v10, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vand.vx v10, v12, a0
; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV32-NEXT: vmv.v.x v12, a0
; CHECK-RV32-NEXT: vand.vi v12, v12, 1
@@ -1924,18 +1964,34 @@ define <8 x i64> @vror_vv_v8i64(<8 x i64> %a, <8 x i64> %b) {
}
define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) {
-; CHECK-LABEL: vror_vx_v8i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: li a0, 63
-; CHECK-NEXT: vand.vx v16, v12, a0
-; CHECK-NEXT: vsrl.vv v16, v8, v16
-; CHECK-NEXT: vrsub.vi v12, v12, 0
-; CHECK-NEXT: vand.vx v12, v12, a0
-; CHECK-NEXT: vsll.vv v8, v8, v12
-; CHECK-NEXT: vor.vv v8, v16, v8
-; CHECK-NEXT: ret
+; CHECK-RV32-LABEL: vror_vx_v8i64:
+; CHECK-RV32: # %bb.0:
+; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vmv.v.x v12, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v16, 0
+; CHECK-RV32-NEXT: vwsub.vx v20, v16, a0
+; CHECK-RV32-NEXT: li a0, 63
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vand.vx v16, v20, a0
+; CHECK-RV32-NEXT: vsll.vv v16, v8, v16
+; CHECK-RV32-NEXT: vand.vx v12, v12, a0
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
+; CHECK-RV32-NEXT: vor.vv v8, v8, v16
+; CHECK-RV32-NEXT: ret
+;
+; CHECK-RV64-LABEL: vror_vx_v8i64:
+; CHECK-RV64: # %bb.0:
+; CHECK-RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
+; CHECK-RV64-NEXT: vmv.v.x v12, a0
+; CHECK-RV64-NEXT: li a0, 63
+; CHECK-RV64-NEXT: vand.vx v16, v12, a0
+; CHECK-RV64-NEXT: vsrl.vv v16, v8, v16
+; CHECK-RV64-NEXT: vrsub.vi v12, v12, 0
+; CHECK-RV64-NEXT: vand.vx v12, v12, a0
+; CHECK-RV64-NEXT: vsll.vv v8, v8, v12
+; CHECK-RV64-NEXT: vor.vv v8, v16, v8
+; CHECK-RV64-NEXT: ret
;
; CHECK-ZVKB-LABEL: vror_vx_v8i64:
; CHECK-ZVKB: # %bb.0:
@@ -1951,11 +2007,13 @@ define <8 x i64> @vror_vx_v8i64(<8 x i64> %a, i64 %b) {
define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_v8i64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-RV32-NEXT: vmv.v.i v12, 1
-; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v12, 0
+; CHECK-RV32-NEXT: li a0, 1
+; CHECK-RV32-NEXT: vwsubu.vx v16, v12, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v12, v12, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vand.vx v12, v16, a0
; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vand.vi v16, v16, 1
@@ -1984,11 +2042,13 @@ define <8 x i64> @vror_vi_v8i64(<8 x i64> %a) {
define <8 x i64> @vror_vi_rotl_v8i64(<8 x i64> %a) {
; CHECK-RV32-LABEL: vror_vi_rotl_v8i64:
; CHECK-RV32: # %bb.0:
-; CHECK-RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
-; CHECK-RV32-NEXT: vmv.v.i v12, 1
-; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v12, 0
+; CHECK-RV32-NEXT: li a0, 1
+; CHECK-RV32-NEXT: vwsubu.vx v16, v12, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v12, v12, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vand.vx v12, v16, a0
; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12
; CHECK-RV32-NEXT: vmv.v.x v16, a0
; CHECK-RV32-NEXT: vand.vi v16, v16, 1
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
index 2a31ff5ab3f8c..3a222e95566a4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwadd.ll
@@ -767,23 +767,13 @@ define <4 x i32> @vwadd_vx_v4i32_i32(ptr %x, ptr %y) {
}
define <2 x i64> @vwadd_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
-; RV32-LABEL: vwadd_vx_v2i64_i8:
-; RV32: # %bb.0:
-; RV32-NEXT: lb a1, 0(a1)
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v9, (a0)
-; RV32-NEXT: vmv.v.x v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vwadd.wv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwadd_vx_v2i64_i8:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: lb a0, 0(a1)
-; RV64-NEXT: vwadd.vx v8, v9, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: vwadd_vx_v2i64_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: lb a0, 0(a1)
+; CHECK-NEXT: vwadd.vx v8, v9, a0
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i8, ptr %y
%c = sext i8 %b to i64
@@ -795,23 +785,13 @@ define <2 x i64> @vwadd_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
}
define <2 x i64> @vwadd_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
-; RV32-LABEL: vwadd_vx_v2i64_i16:
-; RV32: # %bb.0:
-; RV32-NEXT: lh a1, 0(a1)
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v9, (a0)
-; RV32-NEXT: vmv.v.x v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vwadd.wv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwadd_vx_v2i64_i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: lh a0, 0(a1)
-; RV64-NEXT: vwadd.vx v8, v9, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: vwadd_vx_v2i64_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: lh a0, 0(a1)
+; CHECK-NEXT: vwadd.vx v8, v9, a0
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i16, ptr %y
%c = sext i16 %b to i64
@@ -823,23 +803,13 @@ define <2 x i64> @vwadd_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
}
define <2 x i64> @vwadd_vx_v2i64_i32(ptr %x, ptr %y) nounwind {
-; RV32-LABEL: vwadd_vx_v2i64_i32:
-; RV32: # %bb.0:
-; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v9, (a0)
-; RV32-NEXT: vmv.v.x v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vwadd.wv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwadd_vx_v2i64_i32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: lw a0, 0(a1)
-; RV64-NEXT: vwadd.vx v8, v9, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: vwadd_vx_v2i64_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: lw a0, 0(a1)
+; CHECK-NEXT: vwadd.vx v8, v9, a0
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i32, ptr %y
%c = sext i32 %b to i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
index 93927e10e607e..9d63b8f31a3e8 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll
@@ -795,22 +795,13 @@ define <4 x i32> @vwmul_vx_v4i32_i32(ptr %x, ptr %y) {
}
define <2 x i64> @vwmul_vx_v2i64_i8(ptr %x, ptr %y) {
-; RV32-LABEL: vwmul_vx_v2i64_i8:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: lb a0, 0(a1)
-; RV32-NEXT: vsext.vf2 v9, v8
-; RV32-NEXT: vmul.vx v8, v9, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwmul_vx_v2i64_i8:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: lb a0, 0(a1)
-; RV64-NEXT: vwmul.vx v8, v9, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: vwmul_vx_v2i64_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: lb a0, 0(a1)
+; CHECK-NEXT: vwmul.vx v8, v9, a0
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i8, ptr %y
%c = sext i8 %b to i64
@@ -822,22 +813,13 @@ define <2 x i64> @vwmul_vx_v2i64_i8(ptr %x, ptr %y) {
}
define <2 x i64> @vwmul_vx_v2i64_i16(ptr %x, ptr %y) {
-; RV32-LABEL: vwmul_vx_v2i64_i16:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: lh a0, 0(a1)
-; RV32-NEXT: vsext.vf2 v9, v8
-; RV32-NEXT: vmul.vx v8, v9, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwmul_vx_v2i64_i16:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: lh a0, 0(a1)
-; RV64-NEXT: vwmul.vx v8, v9, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: vwmul_vx_v2i64_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: lh a0, 0(a1)
+; CHECK-NEXT: vwmul.vx v8, v9, a0
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i16, ptr %y
%c = sext i16 %b to i64
@@ -849,22 +831,13 @@ define <2 x i64> @vwmul_vx_v2i64_i16(ptr %x, ptr %y) {
}
define <2 x i64> @vwmul_vx_v2i64_i32(ptr %x, ptr %y) {
-; RV32-LABEL: vwmul_vx_v2i64_i32:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: lw a0, 0(a1)
-; RV32-NEXT: vsext.vf2 v9, v8
-; RV32-NEXT: vmul.vx v8, v9, a0
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwmul_vx_v2i64_i32:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: lw a0, 0(a1)
-; RV64-NEXT: vwmul.vx v8, v9, a0
-; RV64-NEXT: ret
+; CHECK-LABEL: vwmul_vx_v2i64_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: lw a0, 0(a1)
+; CHECK-NEXT: vwmul.vx v8, v9, a0
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i32, ptr %y
%c = sext i32 %b to i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
index af67b9920ed1e..fce22849a58af 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsll.ll
@@ -906,19 +906,12 @@ define <4 x i64> @vwsll_vi_v4i64_v4i8(<4 x i8> %a) {
; CHECK-NEXT: vsll.vi v8, v10, 2
; CHECK-NEXT: ret
;
-; CHECK-ZVBB-RV32-LABEL: vwsll_vi_v4i64_v4i8:
-; CHECK-ZVBB-RV32: # %bb.0:
-; CHECK-ZVBB-RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
-; CHECK-ZVBB-RV32-NEXT: vzext.vf8 v10, v8
-; CHECK-ZVBB-RV32-NEXT: vsll.vi v8, v10, 2
-; CHECK-ZVBB-RV32-NEXT: ret
-;
-; CHECK-ZVBB-RV64-LABEL: vwsll_vi_v4i64_v4i8:
-; CHECK-ZVBB-RV64: # %bb.0:
-; CHECK-ZVBB-RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-ZVBB-RV64-NEXT: vzext.vf4 v10, v8
-; CHECK-ZVBB-RV64-NEXT: vwsll.vi v8, v10, 2
-; CHECK-ZVBB-RV64-NEXT: ret
+; CHECK-ZVBB-LABEL: vwsll_vi_v4i64_v4i8:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
+; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
+; CHECK-ZVBB-NEXT: ret
%x = zext <4 x i8> %a to <4 x i64>
%z = shl <4 x i64> %x, splat (i64 2)
ret <4 x i64> %z
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
index c3353a2df4912..d632dc4c2a30d 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub.ll
@@ -770,24 +770,14 @@ define <4 x i32> @vwsub_vx_v4i32_i32(ptr %x, ptr %y) {
}
define <2 x i64> @vwsub_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
-; RV32-LABEL: vwsub_vx_v2i64_i8:
-; RV32: # %bb.0:
-; RV32-NEXT: lb a1, 0(a1)
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v9, (a0)
-; RV32-NEXT: vmv.v.x v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vwsub.wv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwsub_vx_v2i64_i8:
-; RV64: # %bb.0:
-; RV64-NEXT: lb a1, 0(a1)
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
-; RV64-NEXT: vwsub.vv v8, v10, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vwsub_vx_v2i64_i8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lb a1, 0(a1)
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vwsub.vv v8, v10, v9
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i8, ptr %y
%c = sext i8 %b to i64
@@ -799,24 +789,14 @@ define <2 x i64> @vwsub_vx_v2i64_i8(ptr %x, ptr %y) nounwind {
}
define <2 x i64> @vwsub_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
-; RV32-LABEL: vwsub_vx_v2i64_i16:
-; RV32: # %bb.0:
-; RV32-NEXT: lh a1, 0(a1)
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v9, (a0)
-; RV32-NEXT: vmv.v.x v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vwsub.wv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwsub_vx_v2i64_i16:
-; RV64: # %bb.0:
-; RV64-NEXT: lh a1, 0(a1)
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
-; RV64-NEXT: vwsub.vv v8, v10, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vwsub_vx_v2i64_i16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lh a1, 0(a1)
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vwsub.vv v8, v10, v9
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i16, ptr %y
%c = sext i16 %b to i64
@@ -828,24 +808,14 @@ define <2 x i64> @vwsub_vx_v2i64_i16(ptr %x, ptr %y) nounwind {
}
define <2 x i64> @vwsub_vx_v2i64_i32(ptr %x, ptr %y) nounwind {
-; RV32-LABEL: vwsub_vx_v2i64_i32:
-; RV32: # %bb.0:
-; RV32-NEXT: lw a1, 0(a1)
-; RV32-NEXT: vsetivli zero, 2, e64, m1, ta, ma
-; RV32-NEXT: vle32.v v9, (a0)
-; RV32-NEXT: vmv.v.x v8, a1
-; RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
-; RV32-NEXT: vwsub.wv v8, v8, v9
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwsub_vx_v2i64_i32:
-; RV64: # %bb.0:
-; RV64-NEXT: lw a1, 0(a1)
-; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
-; RV64-NEXT: vle32.v v9, (a0)
-; RV64-NEXT: vmv.v.x v10, a1
-; RV64-NEXT: vwsub.vv v8, v10, v9
-; RV64-NEXT: ret
+; CHECK-LABEL: vwsub_vx_v2i64_i32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lw a1, 0(a1)
+; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
+; CHECK-NEXT: vle32.v v9, (a0)
+; CHECK-NEXT: vmv.v.x v10, a1
+; CHECK-NEXT: vwsub.vv v8, v10, v9
+; CHECK-NEXT: ret
%a = load <2 x i32>, ptr %x
%b = load i32, ptr %y
%c = sext i32 %b to i64
diff --git a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
index 4ea5a6709db5c..4a86b717f9f3c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vrol-sdnode.ll
@@ -944,13 +944,16 @@ define <vscale x 1 x i64> @vrol_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v10, 0
+; CHECK-RV32-NEXT: vwsub.vx v11, v10, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v10, v9, a0
-; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
-; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vand.vx v10, v11, a0
+; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
; CHECK-RV32-NEXT: vand.vx v9, v9, a0
-; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
-; CHECK-RV32-NEXT: vor.vv v8, v10, v8
+; CHECK-RV32-NEXT: vsll.vv v8, v8, v9
+; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv1i64:
@@ -1004,13 +1007,16 @@ define <vscale x 2 x i64> @vrol_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v10, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v12, 0
+; CHECK-RV32-NEXT: vwsub.vx v14, v12, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v12, v10, a0
-; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
-; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vand.vx v12, v14, a0
+; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
-; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
-; CHECK-RV32-NEXT: vor.vv v8, v12, v8
+; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
+; CHECK-RV32-NEXT: vor.vv v8, v8, v12
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv2i64:
@@ -1064,13 +1070,16 @@ define <vscale x 4 x i64> @vrol_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v16, 0
+; CHECK-RV32-NEXT: vwsub.vx v20, v16, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v16, v12, a0
-; CHECK-RV32-NEXT: vsll.vv v16, v8, v16
-; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vand.vx v16, v20, a0
+; CHECK-RV32-NEXT: vsrl.vv v16, v8, v16
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
-; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
-; CHECK-RV32-NEXT: vor.vv v8, v16, v8
+; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
+; CHECK-RV32-NEXT: vor.vv v8, v8, v16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv4i64:
@@ -1124,13 +1133,16 @@ define <vscale x 8 x i64> @vrol_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v16, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v24, 0
+; CHECK-RV32-NEXT: vwsub.vx v0, v24, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v24, v16, a0
-; CHECK-RV32-NEXT: vsll.vv v24, v8, v24
-; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT: vand.vx v24, v0, a0
+; CHECK-RV32-NEXT: vsrl.vv v24, v8, v24
; CHECK-RV32-NEXT: vand.vx v16, v16, a0
-; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
-; CHECK-RV32-NEXT: vor.vv v8, v24, v8
+; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
+; CHECK-RV32-NEXT: vor.vv v8, v8, v24
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vrol_vx_nxv8i64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
index 16abf2bd28acc..cf2f0d8873165 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vror-sdnode.ll
@@ -1611,13 +1611,16 @@ define <vscale x 1 x i64> @vror_vx_nxv1i64(<vscale x 1 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v9, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v10, 0
+; CHECK-RV32-NEXT: vwsub.vx v11, v10, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v10, v9, a0
-; CHECK-RV32-NEXT: vsrl.vv v10, v8, v10
-; CHECK-RV32-NEXT: vrsub.vi v9, v9, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m1, ta, ma
+; CHECK-RV32-NEXT: vand.vx v10, v11, a0
+; CHECK-RV32-NEXT: vsll.vv v10, v8, v10
; CHECK-RV32-NEXT: vand.vx v9, v9, a0
-; CHECK-RV32-NEXT: vsll.vv v8, v8, v9
-; CHECK-RV32-NEXT: vor.vv v8, v10, v8
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v9
+; CHECK-RV32-NEXT: vor.vv v8, v8, v10
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vror_vx_nxv1i64:
@@ -1710,13 +1713,16 @@ define <vscale x 2 x i64> @vror_vx_nxv2i64(<vscale x 2 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v10, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m1, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v12, 0
+; CHECK-RV32-NEXT: vwsub.vx v14, v12, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v12, v10, a0
-; CHECK-RV32-NEXT: vsrl.vv v12, v8, v12
-; CHECK-RV32-NEXT: vrsub.vi v10, v10, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m2, ta, ma
+; CHECK-RV32-NEXT: vand.vx v12, v14, a0
+; CHECK-RV32-NEXT: vsll.vv v12, v8, v12
; CHECK-RV32-NEXT: vand.vx v10, v10, a0
-; CHECK-RV32-NEXT: vsll.vv v8, v8, v10
-; CHECK-RV32-NEXT: vor.vv v8, v12, v8
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v10
+; CHECK-RV32-NEXT: vor.vv v8, v8, v12
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vror_vx_nxv2i64:
@@ -1809,13 +1815,16 @@ define <vscale x 4 x i64> @vror_vx_nxv4i64(<vscale x 4 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v12, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v16, 0
+; CHECK-RV32-NEXT: vwsub.vx v20, v16, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v16, v12, a0
-; CHECK-RV32-NEXT: vsrl.vv v16, v8, v16
-; CHECK-RV32-NEXT: vrsub.vi v12, v12, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
+; CHECK-RV32-NEXT: vand.vx v16, v20, a0
+; CHECK-RV32-NEXT: vsll.vv v16, v8, v16
; CHECK-RV32-NEXT: vand.vx v12, v12, a0
-; CHECK-RV32-NEXT: vsll.vv v8, v8, v12
-; CHECK-RV32-NEXT: vor.vv v8, v16, v8
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v12
+; CHECK-RV32-NEXT: vor.vv v8, v8, v16
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vror_vx_nxv4i64:
@@ -1908,13 +1917,16 @@ define <vscale x 8 x i64> @vror_vx_nxv8i64(<vscale x 8 x i64> %a, i64 %b) {
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-RV32-NEXT: vmv.v.x v16, a0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
+; CHECK-RV32-NEXT: vmv.v.i v24, 0
+; CHECK-RV32-NEXT: vwsub.vx v0, v24, a0
; CHECK-RV32-NEXT: li a0, 63
-; CHECK-RV32-NEXT: vand.vx v24, v16, a0
-; CHECK-RV32-NEXT: vsrl.vv v24, v8, v24
-; CHECK-RV32-NEXT: vrsub.vi v16, v16, 0
+; CHECK-RV32-NEXT: vsetvli zero, zero, e64, m8, ta, ma
+; CHECK-RV32-NEXT: vand.vx v24, v0, a0
+; CHECK-RV32-NEXT: vsll.vv v24, v8, v24
; CHECK-RV32-NEXT: vand.vx v16, v16, a0
-; CHECK-RV32-NEXT: vsll.vv v8, v8, v16
-; CHECK-RV32-NEXT: vor.vv v8, v24, v8
+; CHECK-RV32-NEXT: vsrl.vv v8, v8, v16
+; CHECK-RV32-NEXT: vor.vv v8, v8, v24
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vror_vx_nxv8i64:
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
index d70f619c3601a..06b31657e0eca 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwadd-sdnode.ll
@@ -1551,21 +1551,12 @@ define <vscale x 8 x i64> @vwadd_wx_splat_zext(<vscale x 8 x i64> %va, i32 %b) {
}
define <vscale x 8 x i64> @vwadd_vx_splat_sext(<vscale x 8 x i32> %va, i32 %b) {
-; RV32-LABEL: vwadd_vx_splat_sext:
-; RV32: # %bb.0:
-; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
-; RV32-NEXT: vmv.v.x v16, a0
-; RV32-NEXT: vsetvli zero, zero, e32, m4, ta, ma
-; RV32-NEXT: vwadd.wv v16, v16, v8
-; RV32-NEXT: vmv8r.v v8, v16
-; RV32-NEXT: ret
-;
-; RV64-LABEL: vwadd_vx_splat_sext:
-; RV64: # %bb.0:
-; RV64-NEXT: vsetvli a1, zero, e32, m4, ta, ma
-; RV64-NEXT: vwadd.vx v16, v8, a0
-; RV64-NEXT: vmv8r.v v8, v16
-; RV64-NEXT: ret
+; CHECK-LABEL: vwadd_vx_splat_sext:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
+; CHECK-NEXT: vwadd.vx v16, v8, a0
+; CHECK-NEXT: vmv8r.v v8, v16
+; CHECK-NEXT: ret
%sb = sext i32 %b to i64
%head = insertelement <vscale x 8 x i64> poison, i64 %sb, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
index 41ec2fc443d02..ff807adf0e59f 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
@@ -864,20 +864,16 @@ define <vscale x 2 x i64> @vwsll_vi_nxv2i64_nxv2i8(<vscale x 2 x i8> %a) {
; CHECK-NEXT: vsll.vi v8, v10, 2
; CHECK-NEXT: ret
;
-; RV32ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
-; RV32ZVBB: # %bb.0:
-; RV32ZVBB-NEXT: vsetvli a0, zero, e64, m2, ta, ma
-; RV32ZVBB-NEXT: vzext.vf8 v10, v8
-; RV32ZVBB-NEXT: vsll.vi v8, v10, 2
-; RV32ZVBB-NEXT: ret
-;
-; RV64ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
-; RV64ZVBB: # %bb.0:
-; RV64ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
-; RV64ZVBB-NEXT: vzext.vf4 v10, v8
-; RV64ZVBB-NEXT: vwsll.vi v8, v10, 2
-; RV64ZVBB-NEXT: ret
+; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64_nxv2i8:
+; CHECK-ZVBB: # %bb.0:
+; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-ZVBB-NEXT: vzext.vf4 v10, v8
+; CHECK-ZVBB-NEXT: vwsll.vi v8, v10, 2
+; CHECK-ZVBB-NEXT: ret
%x = zext <vscale x 2 x i8> %a to <vscale x 2 x i64>
%z = shl <vscale x 2 x i64> %x, splat (i64 2)
ret <vscale x 2 x i64> %z
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32ZVBB: {{.*}}
+; RV64ZVBB: {{.*}}
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