[llvm] [InstCombine] Select (PR #99245)
Tim Gymnich via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 16 14:32:56 PDT 2024
https://github.com/tgymnich created https://github.com/llvm/llvm-project/pull/99245
None
>From e812b5f12fe1557ebc69c5c09f0eb07388e47427 Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tgymnich at icloud.com>
Date: Sun, 14 Jul 2024 15:33:31 +0200
Subject: [PATCH 1/2] [InstCombine] Add fold for select of symmetric selects
Alive2 proof: https://alive2.llvm.org/ce/z/4QAm4K
---
.../InstCombine/InstCombineSelect.cpp | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 394dfca262e13..67f8986abef36 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -3012,6 +3012,28 @@ struct DecomposedSelect {
};
} // namespace
+/// Folds patterns like:
+/// select c2 (select c1 a b) (select c1 b a)
+/// into:
+/// select (xor c1 c2) b a
+static Instruction *
+foldSelectOfSymmetricSelect(SelectInst &OuterSelVal,
+ InstCombiner::BuilderTy &Builder) {
+
+ DecomposedSelect OuterSel, InnerSel;
+ if (!match(&OuterSelVal, m_Select(m_Value(OuterSel.Cond),
+ m_Select(m_Value(InnerSel.Cond),
+ m_Value(InnerSel.TrueVal),
+ m_Value(InnerSel.FalseVal)),
+ m_Select(m_Deferred(InnerSel.Cond),
+ m_Deferred(InnerSel.FalseVal),
+ m_Deferred(InnerSel.TrueVal)))))
+ return nullptr;
+
+ Value *Xor = Builder.CreateXor(InnerSel.Cond, OuterSel.Cond);
+ return SelectInst::Create(Xor, InnerSel.FalseVal, InnerSel.TrueVal);
+}
+
/// Look for patterns like
/// %outer.cond = select i1 %inner.cond, i1 %alt.cond, i1 false
/// %inner.sel = select i1 %inner.cond, i8 %inner.sel.t, i8 %inner.sel.f
@@ -3987,6 +4009,9 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
}
}
+ if (Instruction *I = foldSelectOfSymmetricSelect(SI, Builder))
+ return I;
+
if (Instruction *I = foldNestedSelects(SI, Builder))
return I;
>From f68723bea240a8fb3b98fc5dd02a48723d09c9ac Mon Sep 17 00:00:00 2001
From: Tim Gymnich <tgymnich at icloud.com>
Date: Sun, 14 Jul 2024 15:47:11 +0200
Subject: [PATCH 2/2] add tests
---
.../select-of-symmetric-selects.ll | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)
create mode 100644 llvm/test/Transforms/InstCombine/select-of-symmetric-selects.ll
diff --git a/llvm/test/Transforms/InstCombine/select-of-symmetric-selects.ll b/llvm/test/Transforms/InstCombine/select-of-symmetric-selects.ll
new file mode 100644
index 0000000000000..9391f841482ae
--- /dev/null
+++ b/llvm/test/Transforms/InstCombine/select-of-symmetric-selects.ll
@@ -0,0 +1,92 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt < %s -passes=instcombine -S | FileCheck %s
+
+define i32 @select_of_symmetric_selects(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[C1:%.*]], [[C2:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[TMP1]], i32 [[B:%.*]], i32 [[A:%.*]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %sel1 = select i1 %c1, i32 %a, i32 %b
+ %sel2 = select i1 %c1, i32 %b, i32 %a
+ %ret = select i1 %c2, i32 %sel1, i32 %sel2
+ ret i32 %ret
+}
+
+define i32 @select_of_symmetric_selects_negative1(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects_negative1(
+; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[C2:%.*]], i32 [[SEL1]], i32 [[A]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %sel1 = select i1 %c1, i32 %a, i32 %b
+ %sel2 = select i1 %c2, i32 %b, i32 %a
+ %ret = select i1 %c2, i32 %sel1, i32 %sel2
+ ret i32 %ret
+}
+
+define i32 @select_of_symmetric_selects_negative2(i32 %a, i32 %b, i32 %c, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects_negative2(
+; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]
+; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C1]], i32 [[B]], i32 [[C:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[C2:%.*]], i32 [[SEL1]], i32 [[SEL2]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %sel1 = select i1 %c1, i32 %a, i32 %b
+ %sel2 = select i1 %c1, i32 %b, i32 %c
+ %ret = select i1 %c2, i32 %sel1, i32 %sel2
+ ret i32 %ret
+}
+
+declare void @use(i32)
+
+define i32 @select_of_symmetric_selects_multi_use(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects_multi_use(
+; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C1:%.*]], i32 [[B:%.*]], i32 [[A:%.*]]
+; CHECK-NEXT: call void @use(i32 [[SEL2]])
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[C1]], [[C2:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[TMP1]], i32 [[B]], i32 [[A]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %sel1 = select i1 %c1, i32 %a, i32 %b
+ %sel2 = select i1 %c1, i32 %b, i32 %a
+ call void @use(i32 %sel2)
+ %ret = select i1 %c2, i32 %sel1, i32 %sel2
+ ret i32 %ret
+}
+
+define i32 @select_of_symmetric_selects_commuted(i32 %a, i32 %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects_commuted(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[C1:%.*]], [[C2:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[TMP1]], i32 [[A:%.*]], i32 [[B:%.*]]
+; CHECK-NEXT: ret i32 [[RET]]
+;
+ %sel1 = select i1 %c1, i32 %a, i32 %b
+ %sel2 = select i1 %c1, i32 %b, i32 %a
+ %ret = select i1 %c2, i32 %sel2, i32 %sel1
+ ret i32 %ret
+}
+
+define <4 x i32> @select_of_symmetric_selects_vector1(<4 x i32> %a, <4 x i32> %b, i1 %c1, i1 %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects_vector1(
+; CHECK-NEXT: [[TMP1:%.*]] = xor i1 [[C1:%.*]], [[C2:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select i1 [[TMP1]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[RET]]
+;
+ %sel1 = select i1 %c1, <4 x i32> %a, <4 x i32> %b
+ %sel2 = select i1 %c1, <4 x i32> %b, <4 x i32> %a
+ %ret = select i1 %c2, <4 x i32> %sel2, <4 x i32> %sel1
+ ret <4 x i32> %ret
+}
+
+define <4 x i32> @select_of_symmetric_selects_vector2(<4 x i32> %a, <4 x i32> %b, <4 x i1> %c1, <4 x i1> %c2) {
+; CHECK-LABEL: @select_of_symmetric_selects_vector2(
+; CHECK-NEXT: [[TMP1:%.*]] = xor <4 x i1> [[C1:%.*]], [[C2:%.*]]
+; CHECK-NEXT: [[RET:%.*]] = select <4 x i1> [[TMP1]], <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]
+; CHECK-NEXT: ret <4 x i32> [[RET]]
+;
+ %sel1 = select <4 x i1> %c1, <4 x i32> %a, <4 x i32> %b
+ %sel2 = select <4 x i1> %c1, <4 x i32> %b, <4 x i32> %a
+ %ret = select <4 x i1> %c2, <4 x i32> %sel2, <4 x i32> %sel1
+ ret <4 x i32> %ret
+}
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