[llvm] [RISCV] Emit VP strided loads/stores in RISCVGatherScatterLowering (PR #98111)

[Philip Reames via llvm-commits]

================
@@ -116,7 +116,7 @@ define void @stride_one_store(i64 %n, ptr %p) {
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetvli a0, zero, e64, m1, ta, ma
 ; RV64-NEXT:    vmv.v.i v8, 0
-; RV64-NEXT:    vs1r.v v8, (a1)
+; RV64-NEXT:    vse64.v v8, (a1)
----------------
preames wrote:

Not saying we need to fix this before landing, but we do need to fix this.  There's an existing combine for converting an element strided riscv_maked_strided_* into a masked_*.  We should replicate that over the vp.strided form before calling the transition complete.  

https://github.com/llvm/llvm-project/pull/98111