[llvm] 78dea4c - [AMDGPU] Use bool literals for bools. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-07-16T15:44:49+01:00
New Revision: 78dea4c1ea77ba683c720d2a2c0f32d03989f8cc

URL: https://github.com/llvm/llvm-project/commit/78dea4c1ea77ba683c720d2a2c0f32d03989f8cc
DIFF: https://github.com/llvm/llvm-project/commit/78dea4c1ea77ba683c720d2a2c0f32d03989f8cc.diff

LOG: [AMDGPU] Use bool literals for bools. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index 86f28a5057694..7a256cf8a9832 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -311,7 +311,7 @@ class PipelineSolver {
   uint64_t BranchesExplored = 0;
 
   // The direction in which we process the candidate SchedGroups per SU
-  bool IsBottomUp = 1;
+  bool IsBottomUp = true;
 
   // Update indices to fit next conflicting instruction
   void advancePosition();
@@ -365,7 +365,7 @@ class PipelineSolver {
 
   PipelineSolver(DenseMap<int, SmallVector<SchedGroup, 4>> &SyncedSchedGroups,
                  DenseMap<int, SUnitsToCandidateSGsMap> &SyncedInstrs,
-                 ScheduleDAGMI *DAG, bool IsBottomUp = 1)
+                 ScheduleDAGMI *DAG, bool IsBottomUp = true)
       : DAG(DAG), SyncedInstrs(SyncedInstrs),
         SyncedSchedGroups(SyncedSchedGroups), IsBottomUp(IsBottomUp) {
 
@@ -858,7 +858,7 @@ class IGLPStrategy {
   virtual bool shouldApplyStrategy(ScheduleDAGInstrs *DAG,
                                    AMDGPU::SchedulingPhase Phase) = 0;
 
-  bool IsBottomUp = 1;
+  bool IsBottomUp = true;
 
   IGLPStrategy(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
       : DAG(DAG), TII(TII) {}
@@ -881,7 +881,7 @@ class MFMASmallGemmOpt final : public IGLPStrategy {
 
   MFMASmallGemmOpt(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
       : IGLPStrategy(DAG, TII) {
-    IsBottomUp = 1;
+    IsBottomUp = true;
   }
 };
 
@@ -1350,7 +1350,7 @@ class MFMAExpInterleaveOpt final : public IGLPStrategy {
 
   MFMAExpInterleaveOpt(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
       : IGLPStrategy(DAG, TII) {
-    IsBottomUp = 0;
+    IsBottomUp = false;
   }
 };
 
@@ -2061,7 +2061,7 @@ class MFMASmallGemmSingleWaveOpt final : public IGLPStrategy {
 
   MFMASmallGemmSingleWaveOpt(ScheduleDAGInstrs *DAG, const SIInstrInfo *TII)
       : IGLPStrategy(DAG, TII) {
-    IsBottomUp = 0;
+    IsBottomUp = false;
   }
 };
 
@@ -2371,7 +2371,7 @@ class IGroupLPDAGMutation : public ScheduleDAGMutation {
   // created SchedGroup first, and will consider that as the ultimate
   // predecessor group when linking. TOP_DOWN instead links and processes the
   // first created SchedGroup first.
-  bool IsBottomUp = 1;
+  bool IsBottomUp = true;
 
   // The scheduling phase this application of IGLP corresponds with.
   AMDGPU::SchedulingPhase Phase = AMDGPU::SchedulingPhase::Initial;