[llvm] 6bba44e - [AMDGPU] Use member initializers. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2024-07-16T15:29:10+01:00
New Revision: 6bba44e8dcf5bb73e6e82068b194b14aa7d1880e

URL: https://github.com/llvm/llvm-project/commit/6bba44e8dcf5bb73e6e82068b194b14aa7d1880e
DIFF: https://github.com/llvm/llvm-project/commit/6bba44e8dcf5bb73e6e82068b194b14aa7d1880e.diff

LOG: [AMDGPU] Use member initializers. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
    llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
    llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
    llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp
    llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
index 3437b6dc8ae0c..dbc9233b72def 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULibFunc.cpp
@@ -367,11 +367,11 @@ static AMDGPULibFunc::Param getRetType(AMDGPULibFunc::EFuncId id,
 class ParamIterator {
   const AMDGPULibFunc::Param (&Leads)[2];
   const ManglingRule& Rule;
-  int Index;
+  int Index = 0;
 public:
   ParamIterator(const AMDGPULibFunc::Param (&leads)[2],
                 const ManglingRule& rule)
-    : Leads(leads), Rule(rule), Index(0) {}
+    : Leads(leads), Rule(rule) {}
 
   AMDGPULibFunc::Param getNextParam();
 };

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
index 470180f2bcd28..6be9be21a8a86 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
@@ -700,7 +700,7 @@ class SplitPtrStructs : public InstVisitor<SplitPtrStructs, PtrParts> {
 
   // Subtarget info, needed for determining what cache control bits to set.
   const TargetMachine *TM;
-  const GCNSubtarget *ST;
+  const GCNSubtarget *ST = nullptr;
 
   IRBuilder<> IRB;
 
@@ -740,7 +740,7 @@ class SplitPtrStructs : public InstVisitor<SplitPtrStructs, PtrParts> {
 
 public:
   SplitPtrStructs(LLVMContext &Ctx, const TargetMachine *TM)
-      : TM(TM), ST(nullptr), IRB(Ctx) {}
+      : TM(TM), IRB(Ctx) {}
 
   void processFunction(Function &F);
 

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
index 31777295b4f8f..99b4fca20bb2d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUMachineFunction.cpp
@@ -44,8 +44,7 @@ AMDGPUMachineFunction::AMDGPUMachineFunction(const Function &F,
     : IsEntryFunction(AMDGPU::isEntryFunctionCC(F.getCallingConv())),
       IsModuleEntryFunction(
           AMDGPU::isModuleEntryFunctionCC(F.getCallingConv())),
-      IsChainFunction(AMDGPU::isChainCC(F.getCallingConv())),
-      NoSignedZerosFPMath(false) {
+      IsChainFunction(AMDGPU::isChainCC(F.getCallingConv())) {
 
   // FIXME: Should initialize KernArgSize based on ExplicitKernelArgOffset,
   // except reserved size is not correctly aligned.

diff  --git a/llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp b/llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp
index a9f1e9bd09963..1213d5e0b41db 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUPerfHintAnalysis.cpp
@@ -68,7 +68,7 @@ struct AMDGPUPerfHint {
 public:
   AMDGPUPerfHint(AMDGPUPerfHintAnalysis::FuncInfoMap &FIM_,
                  const TargetLowering *TLI_)
-      : FIM(FIM_), DL(nullptr), TLI(TLI_) {}
+      : FIM(FIM_), TLI(TLI_) {}
 
   bool runOnFunction(Function &F);
 
@@ -95,7 +95,7 @@ struct AMDGPUPerfHint {
 
   AMDGPUPerfHintAnalysis::FuncInfoMap &FIM;
 
-  const DataLayout *DL;
+  const DataLayout *DL = nullptr;
 
   const TargetLowering *TLI;
 

diff  --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
index 68c5f23c8e11f..d43100254bfc9 100644
--- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
@@ -124,7 +124,7 @@ class SIFixSGPRCopies : public MachineFunctionPass {
   SmallVector<MachineInstr*, 4> RegSequences;
   SmallVector<MachineInstr*, 4> PHINodes;
   SmallVector<MachineInstr*, 4> S2VCopies;
-  unsigned NextVGPRToSGPRCopyID;
+  unsigned NextVGPRToSGPRCopyID = 0;
   MapVector<unsigned, V2SCopyInfo> V2SCopies;
   DenseMap<MachineInstr *, SetVector<unsigned>> SiblingPenalty;
 
@@ -135,7 +135,7 @@ class SIFixSGPRCopies : public MachineFunctionPass {
   const SIRegisterInfo *TRI;
   const SIInstrInfo *TII;
 
-  SIFixSGPRCopies() : MachineFunctionPass(ID), NextVGPRToSGPRCopyID(0) {}
+  SIFixSGPRCopies() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override;
   void fixSCCCopies(MachineFunction &MF);