[llvm] [AArch64] Lower scalable i1 vector add reduction to cntp (PR #99031)

[Sander de Smalen via llvm-commits]

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@@ -0,0 +1,132 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define i8 @uaddv_zexti8_nxv16i1(<vscale x 16 x i1> %v) {
+; CHECK-LABEL: uaddv_zexti8_nxv16i1:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    cntp x0, p0, p0.b
+; CHECK-NEXT:    // kill: def $w0 killed $w0 killed $x0
+; CHECK-NEXT:    ret
+entry:
+  %3 = zext <vscale x 16 x i1> %v to <vscale x 16 x i8>
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sdesmalen-arm wrote:

What would happen for an extend to an i64 element type, e.g. `zext <vscale x 16 x i1> %v to <vscale x 16 x i64>` ?
Could you add a test for this too?

https://github.com/llvm/llvm-project/pull/99031