[llvm] [TTI][WebAssembly] Pairwise reduction expansion (PR #93948)

[Sam Parker via llvm-commits]

sparker-arm wrote:

> is that code the engine is expected to generate correct with respect to the Wasm spec, or is this a method of providing unsafe optimization hints to the engine?

This allows the engine to generate more optimised code while respecting the Wasm spec. The key here is that when compiling with Ofast, LLVM can choose an arbitrary shuffle pattern but once this is lowered to Wasm, it is no longer arbitrary - the engine has to perform the adds in the order specified. By changing the shuffle pattern here, it allows a Wasm engine to select pairwise add vector instructions, such as faddp on AArch64 or haddps on X86.

https://github.com/llvm/llvm-project/pull/93948