[llvm] 4fac145 - [X86] combineSelect - reuse existing SDLoc. NFC.
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Mon Jul 15 08:34:45 PDT 2024
Author: Simon Pilgrim
Date: 2024-07-15T16:34:22+01:00
New Revision: 4fac1456d3132e2745ddbfacb326cf0afd613f3c
URL: https://github.com/llvm/llvm-project/commit/4fac1456d3132e2745ddbfacb326cf0afd613f3c
DIFF: https://github.com/llvm/llvm-project/commit/4fac1456d3132e2745ddbfacb326cf0afd613f3c.diff
LOG: [X86] combineSelect - reuse existing SDLoc. NFC.
Added:
Modified:
llvm/lib/Target/X86/X86ISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 93876fc0876dc..1d947ac2346d0 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45385,7 +45385,7 @@ static SDValue combineToExtendBoolVectorInReg(
/// select to a bitwise logic operation.
/// TODO: Move to DAGCombiner, possibly using TargetLowering::hasAndNot()?
static SDValue
-combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
+combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG, const SDLoc &DL,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
SDValue Cond = N->getOperand(0);
@@ -45393,7 +45393,6 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
SDValue RHS = N->getOperand(2);
EVT VT = LHS.getValueType();
EVT CondVT = Cond.getValueType();
- SDLoc DL(N);
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (N->getOpcode() != ISD::VSELECT)
@@ -45491,7 +45490,7 @@ combineVSelectWithAllOnesOrZeros(SDNode *N, SelectionDAG &DAG,
/// and concatenate the result to eliminate a wide (256-bit) vector instruction:
/// vselect Cond, (concat T0, T1), (concat F0, F1) -->
/// concat (vselect (split Cond), T0, F0), (vselect (split Cond), T1, F1)
-static SDValue narrowVectorSelect(SDNode *N, SelectionDAG &DAG,
+static SDValue narrowVectorSelect(SDNode *N, SelectionDAG &DAG, const SDLoc &DL,
const X86Subtarget &Subtarget) {
unsigned Opcode = N->getOpcode();
if (Opcode != X86ISD::BLENDV && Opcode != ISD::VSELECT)
@@ -45515,15 +45514,15 @@ static SDValue narrowVectorSelect(SDNode *N, SelectionDAG &DAG,
ArrayRef<SDValue> Ops) {
return DAG.getNode(Opcode, DL, Ops[1].getValueType(), Ops);
};
- return SplitOpsAndApply(DAG, Subtarget, SDLoc(N), VT, { Cond, TVal, FVal },
- makeBlend, /*CheckBWI*/ false);
+ return SplitOpsAndApply(DAG, Subtarget, DL, VT, {Cond, TVal, FVal}, makeBlend,
+ /*CheckBWI*/ false);
}
-static SDValue combineSelectOfTwoConstants(SDNode *N, SelectionDAG &DAG) {
+static SDValue combineSelectOfTwoConstants(SDNode *N, SelectionDAG &DAG,
+ const SDLoc &DL) {
SDValue Cond = N->getOperand(0);
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
- SDLoc DL(N);
auto *TrueC = dyn_cast<ConstantSDNode>(LHS);
auto *FalseC = dyn_cast<ConstantSDNode>(RHS);
@@ -45597,6 +45596,7 @@ static SDValue combineSelectOfTwoConstants(SDNode *N, SelectionDAG &DAG) {
/// This function will also call SimplifyDemandedBits on already created
/// BLENDV to perform additional simplifications.
static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
+ const SDLoc &DL,
TargetLowering::DAGCombinerInfo &DCI,
const X86Subtarget &Subtarget) {
SDValue Cond = N->getOperand(0);
@@ -45681,8 +45681,8 @@ static SDValue combineVSelectToBLENDV(SDNode *N, SelectionDAG &DAG,
// Otherwise we can still at least try to simplify multiple use bits.
if (SDValue V = TLI.SimplifyMultipleUseDemandedBits(Cond, DemandedBits, DAG))
- return DAG.getNode(X86ISD::BLENDV, SDLoc(N), N->getValueType(0), V,
- N->getOperand(1), N->getOperand(2));
+ return DAG.getNode(X86ISD::BLENDV, DL, N->getValueType(0), V,
+ N->getOperand(1), N->getOperand(2));
return SDValue();
}
@@ -45749,14 +45749,13 @@ static SDValue combineLogicBlendIntoConditionalNegate(
return DAG.getBitcast(VT, Res);
}
-static SDValue commuteSelect(SDNode *N, SelectionDAG &DAG,
- const X86Subtarget &Subtarget) {
+static SDValue commuteSelect(SDNode *N, SelectionDAG &DAG, const SDLoc &DL,
+ const X86Subtarget &Subtarget) {
if (!Subtarget.hasAVX512())
return SDValue();
if (N->getOpcode() != ISD::VSELECT)
return SDValue();
- SDLoc DL(N);
SDValue Cond = N->getOperand(0);
SDValue LHS = N->getOperand(1);
SDValue RHS = N->getOperand(2);
@@ -45798,7 +45797,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// folded with mask instruction, while the rhs operand can't. Commute the
// lhs and rhs of the select instruction to create the opportunity of
// folding.
- if (SDValue V = commuteSelect(N, DAG, Subtarget))
+ if (SDValue V = commuteSelect(N, DAG, DL, Subtarget))
return V;
EVT VT = LHS.getValueType();
@@ -46080,7 +46079,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
}
}
- if (SDValue V = combineSelectOfTwoConstants(N, DAG))
+ if (SDValue V = combineSelectOfTwoConstants(N, DAG, DL))
return V;
if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
@@ -46222,13 +46221,13 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
if (!TLI.isTypeLegal(VT) || isSoftF16(VT, Subtarget))
return SDValue();
- if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DCI, Subtarget))
+ if (SDValue V = combineVSelectWithAllOnesOrZeros(N, DAG, DL, DCI, Subtarget))
return V;
- if (SDValue V = combineVSelectToBLENDV(N, DAG, DCI, Subtarget))
+ if (SDValue V = combineVSelectToBLENDV(N, DAG, DL, DCI, Subtarget))
return V;
- if (SDValue V = narrowVectorSelect(N, DAG, Subtarget))
+ if (SDValue V = narrowVectorSelect(N, DAG, DL, Subtarget))
return V;
// select(~Cond, X, Y) -> select(Cond, Y, X)
More information about the llvm-commits
mailing list