[llvm] 8da3852 - Revert "[AMDGPU] Generate test fix-wwm-vgpr-copy.ll (NFC)"
Carl Ritson via llvm-commits
llvm-commits at lists.llvm.org
Sun Jul 14 21:07:48 PDT 2024
Author: Carl Ritson
Date: 2024-07-15T13:07:32+09:00
New Revision: 8da3852f44c64ac4535128741695b9e9d8ee27ef
URL: https://github.com/llvm/llvm-project/commit/8da3852f44c64ac4535128741695b9e9d8ee27ef
DIFF: https://github.com/llvm/llvm-project/commit/8da3852f44c64ac4535128741695b9e9d8ee27ef.diff
LOG: Revert "[AMDGPU] Generate test fix-wwm-vgpr-copy.ll (NFC)"
This reverts commit 5c8eb83ce8e4ef40fbd61a05f1de6394eb908da4.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll b/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
index a9a500d110027..9b20d9be278c6 100644
--- a/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
+++ b/llvm/test/CodeGen/AMDGPU/fix-wwm-vgpr-copy.ll
@@ -1,37 +1,9 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; NOTE: llvm.amdgcn.wwm is deprecated, use llvm.amdgcn.strict.wwm instead.
; GCN-LABEL: wwm:
define amdgpu_hs void @wwm(i32 inreg %arg, ptr addrspace(8) inreg %buffer) {
-; GCN-LABEL: wwm:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_mov_b32 s7, s4
-; GCN-NEXT: s_mov_b32 s6, s3
-; GCN-NEXT: s_mov_b32 s5, s2
-; GCN-NEXT: s_mov_b32 s4, s1
-; GCN-NEXT: s_mov_b32 s1, 1
-; GCN-NEXT: v_mov_b32_e32 v0, 4
-; GCN-NEXT: s_not_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v0, 1
-; GCN-NEXT: s_not_b64 exec, exec
-; GCN-NEXT: s_or_saveexec_b64 s[2:3], -1
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_mov_b64 exec, s[2:3]
-; GCN-NEXT: s_cmp_lg_u32 s0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, v0
-; GCN-NEXT: s_cbranch_scc0 .LBB0_2
-; GCN-NEXT: ; %bb.1: ; %bb42
-; GCN-NEXT: s_mov_b32 s1, 0
-; GCN-NEXT: .LBB0_2: ; %bb602
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1
-; GCN-NEXT: s_cbranch_vccnz .LBB0_4
-; GCN-NEXT: ; %bb.3: ; %bb49
-; GCN-NEXT: v_mov_b32_e32 v1, 1.0
-; GCN-NEXT: tbuffer_store_format_x v1, off, s[4:7], 1 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] offset:4 glc
-; GCN-NEXT: .LBB0_4: ; %bb54
-; GCN-NEXT: s_endpgm
entry:
br label %work
@@ -51,10 +23,16 @@ bb54:
ret void
work:
+; GCN: s_not_b64 exec, exec
+; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1
+; GCN: s_not_b64 exec, exec
%tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)
+; GCN: s_or_saveexec_b64 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], -1
+; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]]
%tmp1191 = mul i32 %tmp1189, 4
+; GCN: s_mov_b64 exec, s[[[LO]]:[[HI]]]
%tmp1196 = tail call i32 @llvm.amdgcn.wwm.i32(i32 %tmp1191)
%tmp34 = icmp eq i32 %arg, 0
@@ -63,33 +41,6 @@ work:
; GCN-LABEL: strict_wwm:
define amdgpu_hs void @strict_wwm(i32 inreg %arg, ptr addrspace(8) inreg %buffer) {
-; GCN-LABEL: strict_wwm:
-; GCN: ; %bb.0: ; %entry
-; GCN-NEXT: s_mov_b32 s7, s4
-; GCN-NEXT: s_mov_b32 s6, s3
-; GCN-NEXT: s_mov_b32 s5, s2
-; GCN-NEXT: s_mov_b32 s4, s1
-; GCN-NEXT: s_mov_b32 s1, 1
-; GCN-NEXT: v_mov_b32_e32 v0, 4
-; GCN-NEXT: s_not_b64 exec, exec
-; GCN-NEXT: v_mov_b32_e32 v0, 1
-; GCN-NEXT: s_not_b64 exec, exec
-; GCN-NEXT: s_or_saveexec_b64 s[2:3], -1
-; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0
-; GCN-NEXT: s_mov_b64 exec, s[2:3]
-; GCN-NEXT: s_cmp_lg_u32 s0, 0
-; GCN-NEXT: v_mov_b32_e32 v1, v0
-; GCN-NEXT: s_cbranch_scc0 .LBB1_2
-; GCN-NEXT: ; %bb.1: ; %bb42
-; GCN-NEXT: s_mov_b32 s1, 0
-; GCN-NEXT: .LBB1_2: ; %bb602
-; GCN-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1
-; GCN-NEXT: s_cbranch_vccnz .LBB1_4
-; GCN-NEXT: ; %bb.3: ; %bb49
-; GCN-NEXT: v_mov_b32_e32 v1, 1.0
-; GCN-NEXT: tbuffer_store_format_x v1, off, s[4:7], 1 format:[BUF_DATA_FORMAT_32,BUF_NUM_FORMAT_FLOAT] offset:4 glc
-; GCN-NEXT: .LBB1_4: ; %bb54
-; GCN-NEXT: s_endpgm
entry:
br label %work
@@ -109,10 +60,16 @@ bb54:
ret void
work:
+; GCN: s_not_b64 exec, exec
+; GCN: v_mov_b32_e32 v[[tmp1189:[0-9]+]], 1
+; GCN: s_not_b64 exec, exec
%tmp1189 = tail call i32 @llvm.amdgcn.set.inactive.i32(i32 4, i32 1)
+; GCN: s_or_saveexec_b64 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], -1
+; GCN: v_lshlrev_b32_e32 v[[tmp1191:[0-9]+]], 2, v[[tmp1189]]
%tmp1191 = mul i32 %tmp1189, 4
+; GCN: s_mov_b64 exec, s[[[LO]]:[[HI]]]
%tmp1196 = tail call i32 @llvm.amdgcn.strict.wwm.i32(i32 %tmp1191)
%tmp34 = icmp eq i32 %arg, 0
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