[llvm] [NVPTX] Lower -1/x to neg.f64(rcp.rn.f64) instead of fdiv (PR #98343)

[Rajat Bajpai via llvm-commits]

https://github.com/rajatbajpai updated https://github.com/llvm/llvm-project/pull/98343

>From 2f071f59b563f4c49bfbeae4d99a303d19fbc281 Mon Sep 17 00:00:00 2001
From: rbajpai <rbajpai at nvidia.com>
Date: Wed, 10 Jul 2024 12:35:55 +0530
Subject: [PATCH] [NVPTX] Lower -1/x to neg.f64(recp.rn.f64) instead of fdiv

The NVPTX backend lowers 1/x to rcp.rn.f64 instruction instead
of slower fdiv instruction. However, in the case of -1/x, it uses the
slower fdiv instruction. After this change, -1/x will be lowered
into neg.f64 (rcp.rn.f64).
---
 llvm/lib/Target/NVPTX/NVPTXInstrInfo.td | 17 +++++++++++++
 llvm/test/CodeGen/NVPTX/rcp-opt.ll      | 34 +++++++++++++++++++++++++
 2 files changed, 51 insertions(+)
 create mode 100644 llvm/test/CodeGen/NVPTX/rcp-opt.ll

diff --git a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
index 827febe845a4c..cd17a9de541ad 100644
--- a/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ b/llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -1150,6 +1150,18 @@ def DoubleConst1 : PatLeaf<(fpimm), [{
   return &N->getValueAPF().getSemantics() == &llvm::APFloat::IEEEdouble() &&
          N->getValueAPF().convertToDouble() == 1.0;
 }]>;
+// Constant -1.0 (double)
+def DoubleConstNeg1 : PatLeaf<(fpimm), [{
+  return &N->getValueAPF().getSemantics() == &llvm::APFloat::IEEEdouble() &&
+         N->getValueAPF().convertToDouble() == -1.0;
+}]>;
+
+
+// Constant -X -> X (double)
+def NegDoubleConst : SDNodeXForm<fpimm, [{
+  return CurDAG->getTargetConstantFP(-(N->getValueAPF()),
+                                     SDLoc(N), MVT::f64);
+}]>;
 
 // Loads FP16 constant into a register.
 //
@@ -1225,6 +1237,11 @@ def FDIV64ri :
             "div.rn.f64 \t$dst, $a, $b;",
             [(set Float64Regs:$dst, (fdiv Float64Regs:$a, fpimm:$b))]>;
 
+// fdiv will be converted to rcp
+// fneg (fdiv 1.0, X) => fneg (rcp.rn X)
+def : Pat<(fdiv DoubleConstNeg1:$a, Float64Regs:$b),
+          (FNEGf64 (FDIV641r (NegDoubleConst node:$a), Float64Regs:$b))>;
+
 //
 // F32 Approximate reciprocal
 //
diff --git a/llvm/test/CodeGen/NVPTX/rcp-opt.ll b/llvm/test/CodeGen/NVPTX/rcp-opt.ll
new file mode 100644
index 0000000000000..c320d3551943f
--- /dev/null
+++ b/llvm/test/CodeGen/NVPTX/rcp-opt.ll
@@ -0,0 +1,34 @@
+; RUN: llc < %s -march=nvptx64 | FileCheck %s
+; RUN: %if ptxas %{ llc < %s -march=nvptx64 | %ptxas-verify %}
+
+;; Check if fneg (fdiv 1, X) lowers to fneg (rcp.rn X).
+
+; CHECK-LABEL: .func{{.*}}test1
+define double @test1(double %in) {
+; CHECK: rcp.rn.f64 [[RCP:%.*]], [[X:%.*]];
+; CHECK-NEXT: neg.f64 [[FNEG:%.*]], [[RCP]];
+  %div = fdiv double 1.000000e+00, %in
+  %neg = fsub double -0.000000e+00, %div
+  ret double %neg
+}
+
+;; Check if fdiv -1, X lowers to fneg (rcp.rn X).
+
+; CHECK-LABEL: .func{{.*}}test2
+define double @test2(double %in) {
+; CHECK: rcp.rn.f64 [[RCP:%.*]], [[X:%.*]];
+; CHECK-NEXT: neg.f64 [[FNEG:%.*]], [[RCP]];
+  %div = fdiv double -1.000000e+00, %in
+  ret double %div
+}
+
+;; Check if fdiv 1, (fneg X) lowers to fneg (rcp.rn X).
+
+; CHECK-LABEL: .func{{.*}}test3
+define double @test3(double %in) {
+; CHECK: rcp.rn.f64 [[RCP:%.*]], [[X:%.*]];
+; CHECK-NEXT: neg.f64 [[FNEG:%.*]], [[RCP]];
+  %neg = fsub double -0.000000e+00, %in
+  %div = fdiv double 1.000000e+00, %neg
+  ret double %div
+}