[llvm] [AArch64] Remove redundant instructions in int-to-fp of lowest vector… (PR #98602)

[via llvm-commits]

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@@ -6068,6 +6068,32 @@ def : Pat<(f16 (any_sint_to_fp (i32 (any_fp_to_sint f16:$Rn)))),
 def : Pat<(f16 (any_uint_to_fp (i32 (any_fp_to_uint f16:$Rn)))),
           (UCVTFv1i16 (f16 (FCVTZUv1f16 f16:$Rn)))>;
 }
+
+// int -> float conversion of value in lane 0 of simd vector should use 
+// correct cvtf variant to avoid costly fpr <-> gpr register transfers.
+def : Pat<(f32 (sint_to_fp (i32 (vector_extract (v4i32 FPR128:$Rn), (i64 0))))),
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SpencerAbson wrote:

Apologies if my comment was unclear, these patterns already fall in the scope of a previous `let Predicates = [HasNEONandIsStreamingSafe]` binding. I can always another guard above these patterns if we'd like this to be clearer?

https://github.com/llvm/llvm-project/pull/98602