[llvm] [NVPTX] Propagate truncate to operands (PR #98666)

[Justin Fargnoli via llvm-commits]

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@@ -5541,6 +5541,53 @@ static SDValue PerformREMCombine(SDNode *N,
   return SDValue();
 }
 
+// truncate (logic_op x, y) --> logic_op (truncate x), (truncate y)
+// This will reduce register pressure.
+static SDValue PerformTruncCombine(SDNode *N,
+                                   TargetLowering::DAGCombinerInfo &DCI) {
+  if (!DCI.isBeforeLegalizeOps())
+    return SDValue();
+
+  SDValue LogicalOp = N->getOperand(0);
+  switch (LogicalOp.getOpcode()) {
+  default:
+    break;
+  case ISD::ADD:
+  case ISD::SUB:
+  case ISD::MUL:
+  case ISD::AND:
+  case ISD::OR:
+  case ISD::XOR: {
+    EVT VT = N->getValueType(0);
+    EVT LogicalVT = LogicalOp.getValueType();
+    if (VT != MVT::i32 || LogicalVT != MVT::i64)
+      break;
+    const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
+    if (!VT.isScalarInteger() &&
+        !TLI.isOperationLegal(LogicalOp.getOpcode(), VT))
+      break;
+    if (!all_of(LogicalOp.getNode()->uses(), [](SDNode *U) {
+          return U->isMachineOpcode()
----------------
justinfargnoli wrote:

[InstCombine](https://github.com/llvm/llvm-project/blob/2ad7b4af95bc333d8f216915cd1b9d688590dcc5/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp#L1822) and [DAGCombiner](https://github.com/llvm/llvm-project/blob/2ad7b4af95bc333d8f216915cd1b9d688590dcc5/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L5822) prefer the opposite transformation (i.e `logic(trunc(A), trunc(B)) -> trunc(logic(A, B))`). 

The code in `DAGCombiner` could be guarded with a `TTI` call. However, [it looks like that wouldn't be possible](https://github.com/llvm/llvm-project/blob/2ad7b4af95bc333d8f216915cd1b9d688590dcc5/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h#L49) for `InstCombine`. 

Do you know another IR-level pass in which this transformation would fit? Otherwise, as you suggested, I'm leaning toward implementing it in DAGToDAG combine. 

https://github.com/llvm/llvm-project/pull/98666