[llvm] [AMDGPU] Re-enable atomic optimization of uniform fadd/fsub with result (PR #97604)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 12 08:31:28 PDT 2024
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/97604
>From 0f7c8375cc3a35c8eda9e0e9c855cf0fd4ec4fc1 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Wed, 3 Jul 2024 17:23:19 +0100
Subject: [PATCH] [AMDGPU] Re-enable atomic optimization of uniform fadd/fsub
with result
Fix various problems to do with the first active lane of the result of
optimized fp atomics, as explained in the comment.
---
.../Target/AMDGPU/AMDGPUAtomicOptimizer.cpp | 28 +-
.../GlobalISel/global-atomic-fadd.f32-rtn.ll | 18 +-
.../AMDGPU/global-atomic-fadd.f32-rtn.ll | 53 +-
.../global-atomicrmw-fadd-wrong-subtarget.ll | 73 +-
.../AMDGPU/global_atomic_optimizer_fp_rtn.ll | 1234 +++++-----
.../CodeGen/AMDGPU/local-atomicrmw-fadd.ll | 2094 ++++++++---------
6 files changed, 1790 insertions(+), 1710 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
index 54968be677a37..3391e8d837ea3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUAtomicOptimizer.cpp
@@ -226,13 +226,6 @@ void AMDGPUAtomicOptimizerImpl::visitAtomicRMWInst(AtomicRMWInst &I) {
bool ValDivergent = UA->isDivergentUse(I.getOperandUse(ValIdx));
- if ((Op == AtomicRMWInst::FAdd || Op == AtomicRMWInst::FSub) &&
- !I.use_empty()) {
- // Disable the uniform return value calculation using fmul because it
- // mishandles infinities, NaNs and signed zeros. FIXME.
- ValDivergent = true;
- }
-
// If the value operand is divergent, each lane is contributing a different
// value to the atomic calculation. We can only optimize divergent values if
// we have DPP available on our subtarget, and the atomic operation is 32
@@ -995,18 +988,25 @@ void AMDGPUAtomicOptimizerImpl::optimizeAtomic(Instruction &I,
break;
case AtomicRMWInst::FAdd:
case AtomicRMWInst::FSub: {
- // FIXME: This path is currently disabled in visitAtomicRMWInst because
- // of problems calculating the first active lane of the result (where
- // Mbcnt is 0):
- // - If V is infinity or NaN we will return NaN instead of BroadcastI.
- // - If BroadcastI is -0.0 and V is positive we will return +0.0 instead
- // of -0.0.
LaneOffset = B.CreateFMul(V, Mbcnt);
break;
}
}
}
- Value *const Result = buildNonAtomicBinOp(B, Op, BroadcastI, LaneOffset);
+ Value *Result = buildNonAtomicBinOp(B, Op, BroadcastI, LaneOffset);
+ if (isAtomicFloatingPointTy) {
+ // For fadd/fsub the first active lane of LaneOffset should be the
+ // identity (-0.0 for fadd or +0.0 for fsub) but the value we calculated
+ // is V * +0.0 which might have the wrong sign or might be nan (if V is
+ // inf or nan).
+ //
+ // For all floating point ops if the in-memory value was a nan then the
+ // binop we just built might have quieted it or changed its payload.
+ //
+ // Correct all these problems by using BroadcastI as the result in the
+ // first active lane.
+ Result = B.CreateSelect(Cond, BroadcastI, Result);
+ }
if (IsPixelShader) {
// Need a final PHI to reconverge to above the helper lane branch mask.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
index 077aff46839a6..b2f6c10ef9066 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
@@ -222,7 +222,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: bb.4.Flow:
; GFX90A-NEXT: successors: %bb.6(0x80000000)
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %43, %bb.5, [[DEF]], %bb.1
+ ; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %44, %bb.5, [[DEF]], %bb.1
; GFX90A-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.6
; GFX90A-NEXT: {{ $}}
@@ -235,9 +235,11 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: [[STRICT_WWM1:%[0-9]+]]:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
; GFX90A-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
; GFX90A-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY21]], 0, [[STRICT_WWM1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX90A-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_6]], 0, [[COPY22]], [[V_CMP_EQ_U32_e64_]], implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.4
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: bb.6 (%ir-block.46):
+ ; GFX90A-NEXT: bb.6 (%ir-block.47):
; GFX90A-NEXT: $vgpr0 = COPY [[PHI]]
; GFX90A-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
@@ -314,7 +316,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX940-NEXT: bb.4.Flow:
; GFX940-NEXT: successors: %bb.6(0x80000000)
; GFX940-NEXT: {{ $}}
- ; GFX940-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %42, %bb.5, [[DEF]], %bb.1
+ ; GFX940-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %43, %bb.5, [[DEF]], %bb.1
; GFX940-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX940-NEXT: S_BRANCH %bb.6
; GFX940-NEXT: {{ $}}
@@ -327,9 +329,11 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX940-NEXT: [[STRICT_WWM1:%[0-9]+]]:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
; GFX940-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
; GFX940-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY21]], 0, [[STRICT_WWM1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX940-NEXT: [[COPY22:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX940-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_6]], 0, [[COPY22]], [[V_CMP_EQ_U32_e64_]], implicit $exec
; GFX940-NEXT: S_BRANCH %bb.4
; GFX940-NEXT: {{ $}}
- ; GFX940-NEXT: bb.6 (%ir-block.46):
+ ; GFX940-NEXT: bb.6 (%ir-block.47):
; GFX940-NEXT: $vgpr0 = COPY [[PHI]]
; GFX940-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
;
@@ -401,7 +405,7 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: bb.4.Flow:
; GFX11-NEXT: successors: %bb.6(0x80000000)
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %41, %bb.5, [[DEF]], %bb.1
+ ; GFX11-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI %42, %bb.5, [[DEF]], %bb.1
; GFX11-NEXT: SI_END_CF [[SI_IF]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.6
; GFX11-NEXT: {{ $}}
@@ -414,9 +418,11 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: [[STRICT_WWM1:%[0-9]+]]:vgpr_32 = STRICT_WWM [[V_WRITELANE_B32_]], implicit $exec
; GFX11-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
; GFX11-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY15]], 0, [[STRICT_WWM1]], 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX11-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_ADD_F32_e64_5]], 0, [[COPY16]], [[V_CMP_EQ_U32_e64_]], implicit $exec
; GFX11-NEXT: S_BRANCH %bb.4
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: bb.6 (%ir-block.47):
+ ; GFX11-NEXT: bb.6 (%ir-block.48):
; GFX11-NEXT: $vgpr0 = COPY [[PHI]]
; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%ret = atomicrmw fadd ptr addrspace(1) %ptr, float %data syncscope("wavefront") monotonic
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
index d4dee983d4fc0..e897bcd9950b9 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomic-fadd.f32-rtn.ll
@@ -200,22 +200,23 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32 = V_READLANE_B32 [[V_ADD_F32_e64_5]], killed [[S_MOV_B32_2]]
; GFX90A-NEXT: early-clobber %2:sgpr_32 = STRICT_WWM killed [[V_READLANE_B32_]], implicit $exec
; GFX90A-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_HI_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec
+ ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vreg_1 = COPY [[V_CMP_EQ_U32_e64_]]
; GFX90A-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
- ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX90A-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.2
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2 (%ir-block.36):
; GFX90A-NEXT: successors: %bb.4(0x80000000)
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX90A-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY %2
- ; GFX90A-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN killed [[V_MOV_B32_e32_1]], [[COPY8]], [[COPY3]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
+ ; GFX90A-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY %2
+ ; GFX90A-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN killed [[V_MOV_B32_e32_1]], [[COPY9]], [[COPY3]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX90A-NEXT: S_BRANCH %bb.4
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.3.Flow:
; GFX90A-NEXT: successors: %bb.5(0x80000000)
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %7, %bb.4
+ ; GFX90A-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %8, %bb.4
; GFX90A-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.5
; GFX90A-NEXT: {{ $}}
@@ -225,11 +226,14 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX90A-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[DEF1]], %bb.1, [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN]], %bb.2
; GFX90A-NEXT: SI_END_CF [[SI_IF1]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX90A-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
- ; GFX90A-NEXT: early-clobber %45:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
- ; GFX90A-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[V_READFIRSTLANE_B32_]], 0, killed %45, 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: early-clobber %46:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
+ ; GFX90A-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_READFIRSTLANE_B32_]], 0, killed %46, 0, 0, implicit $mode, implicit $exec
+ ; GFX90A-NEXT: [[COPY10:%[0-9]+]]:sreg_64_xexec = COPY [[COPY8]]
+ ; GFX90A-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX90A-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, killed [[V_ADD_F32_e64_6]], 0, [[COPY11]], [[COPY10]], implicit $exec
; GFX90A-NEXT: S_BRANCH %bb.3
; GFX90A-NEXT: {{ $}}
- ; GFX90A-NEXT: bb.5 (%ir-block.46):
+ ; GFX90A-NEXT: bb.5 (%ir-block.47):
; GFX90A-NEXT: $vgpr0 = COPY [[PHI]]
; GFX90A-NEXT: SI_RETURN_TO_EPILOG $vgpr0
;
@@ -278,22 +282,23 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX940-NEXT: [[V_READLANE_B32_:%[0-9]+]]:sreg_32 = V_READLANE_B32 [[V_ADD_F32_e64_5]], killed [[S_MOV_B32_2]]
; GFX940-NEXT: early-clobber %2:sgpr_32 = STRICT_WWM killed [[V_READLANE_B32_]], implicit $exec
; GFX940-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_HI_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec
+ ; GFX940-NEXT: [[COPY8:%[0-9]+]]:vreg_1 = COPY [[V_CMP_EQ_U32_e64_]]
; GFX940-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
- ; GFX940-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX940-NEXT: [[SI_IF1:%[0-9]+]]:sreg_64 = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX940-NEXT: S_BRANCH %bb.2
; GFX940-NEXT: {{ $}}
; GFX940-NEXT: bb.2 (%ir-block.36):
; GFX940-NEXT: successors: %bb.4(0x80000000)
; GFX940-NEXT: {{ $}}
; GFX940-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX940-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY %2
- ; GFX940-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN killed [[V_MOV_B32_e32_1]], [[COPY8]], [[COPY3]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
+ ; GFX940-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY %2
+ ; GFX940-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN killed [[V_MOV_B32_e32_1]], [[COPY9]], [[COPY3]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX940-NEXT: S_BRANCH %bb.4
; GFX940-NEXT: {{ $}}
; GFX940-NEXT: bb.3.Flow:
; GFX940-NEXT: successors: %bb.5(0x80000000)
; GFX940-NEXT: {{ $}}
- ; GFX940-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %7, %bb.4
+ ; GFX940-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %8, %bb.4
; GFX940-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX940-NEXT: S_BRANCH %bb.5
; GFX940-NEXT: {{ $}}
@@ -303,11 +308,14 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX940-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[DEF1]], %bb.1, [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN]], %bb.2
; GFX940-NEXT: SI_END_CF [[SI_IF1]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX940-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
- ; GFX940-NEXT: early-clobber %44:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
- ; GFX940-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[V_READFIRSTLANE_B32_]], 0, killed %44, 0, 0, implicit $mode, implicit $exec
+ ; GFX940-NEXT: early-clobber %45:vgpr_32 = STRICT_WWM [[V_MOV_B32_dpp6]], implicit $exec
+ ; GFX940-NEXT: [[V_ADD_F32_e64_6:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_READFIRSTLANE_B32_]], 0, killed %45, 0, 0, implicit $mode, implicit $exec
+ ; GFX940-NEXT: [[COPY10:%[0-9]+]]:sreg_64_xexec = COPY [[COPY8]]
+ ; GFX940-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[V_READFIRSTLANE_B32_]]
+ ; GFX940-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, killed [[V_ADD_F32_e64_6]], 0, [[COPY11]], [[COPY10]], implicit $exec
; GFX940-NEXT: S_BRANCH %bb.3
; GFX940-NEXT: {{ $}}
- ; GFX940-NEXT: bb.5 (%ir-block.46):
+ ; GFX940-NEXT: bb.5 (%ir-block.47):
; GFX940-NEXT: $vgpr0 = COPY [[PHI]]
; GFX940-NEXT: SI_RETURN_TO_EPILOG $vgpr0
;
@@ -356,22 +364,23 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: [[V_READLANE_B32_1:%[0-9]+]]:sreg_32 = V_READLANE_B32 [[V_ADD_F32_e64_4]], killed [[S_MOV_B32_5]]
; GFX11-NEXT: early-clobber %2:sgpr_32 = STRICT_WWM killed [[V_READLANE_B32_1]], implicit $exec
; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32 = V_CMP_EQ_U32_e64 killed [[V_MBCNT_LO_U32_B32_e64_]], [[S_MOV_B32_]], implicit $exec
+ ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vreg_1 = COPY [[V_CMP_EQ_U32_e64_]]
; GFX11-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF
- ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF killed [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
+ ; GFX11-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32 = SI_IF [[V_CMP_EQ_U32_e64_]], %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.2
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.2 (%ir-block.36):
; GFX11-NEXT: successors: %bb.4(0x80000000)
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
- ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY %2
- ; GFX11-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN killed [[V_MOV_B32_e32_1]], [[COPY5]], [[COPY3]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
+ ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY %2
+ ; GFX11-NEXT: [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_F32_SADDR_RTN killed [[V_MOV_B32_e32_1]], [[COPY6]], [[COPY3]], 0, 1, implicit $exec :: (load store syncscope("wavefront") monotonic (s32) on %ir.ptr, addrspace 1)
; GFX11-NEXT: S_BRANCH %bb.4
; GFX11-NEXT: {{ $}}
; GFX11-NEXT: bb.3.Flow:
; GFX11-NEXT: successors: %bb.5(0x80000000)
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %7, %bb.4
+ ; GFX11-NEXT: [[PHI:%[0-9]+]]:vgpr_32 = PHI [[DEF]], %bb.0, %8, %bb.4
; GFX11-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: S_BRANCH %bb.5
; GFX11-NEXT: {{ $}}
@@ -381,11 +390,13 @@ define amdgpu_ps float @global_atomic_fadd_f32_saddr_rtn_atomicrmw(ptr addrspace
; GFX11-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[DEF1]], %bb.1, [[GLOBAL_ATOMIC_ADD_F32_SADDR_RTN]], %bb.2
; GFX11-NEXT: SI_END_CF [[SI_IF1]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec
; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32 = V_READFIRSTLANE_B32 [[PHI1]], implicit $exec
- ; GFX11-NEXT: early-clobber %44:vgpr_32 = STRICT_WWM [[V_WRITELANE_B32_]], implicit $exec
- ; GFX11-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, killed [[V_READFIRSTLANE_B32_]], 0, killed %44, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: early-clobber %45:vgpr_32 = STRICT_WWM [[V_WRITELANE_B32_]], implicit $exec
+ ; GFX11-NEXT: [[V_ADD_F32_e64_5:%[0-9]+]]:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[V_READFIRSTLANE_B32_]], 0, killed %45, 0, 0, implicit $mode, implicit $exec
+ ; GFX11-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec = COPY [[COPY5]]
+ ; GFX11-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, killed [[V_ADD_F32_e64_5]], 0, [[V_READFIRSTLANE_B32_]], [[COPY7]], implicit $exec
; GFX11-NEXT: S_BRANCH %bb.3
; GFX11-NEXT: {{ $}}
- ; GFX11-NEXT: bb.5 (%ir-block.47):
+ ; GFX11-NEXT: bb.5 (%ir-block.48):
; GFX11-NEXT: $vgpr0 = COPY [[PHI]]
; GFX11-NEXT: SI_RETURN_TO_EPILOG $vgpr0
%ret = atomicrmw fadd ptr addrspace(1) %ptr, float %data syncscope("wavefront") monotonic
diff --git a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
index 32c2078f08fc0..be6f8a4375163 100644
--- a/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
+++ b/llvm/test/CodeGen/AMDGPU/global-atomicrmw-fadd-wrong-subtarget.ll
@@ -4,55 +4,44 @@
define amdgpu_kernel void @global_atomic_fadd_ret_f32_wrong_subtarget(ptr addrspace(1) %ptr) #1 {
; GCN-LABEL: global_atomic_fadd_ret_f32_wrong_subtarget:
; GCN: ; %bb.0:
-; GCN-NEXT: s_mov_b64 s[2:3], exec
-; GCN-NEXT: v_bfrev_b32_e32 v1, 1
-; GCN-NEXT: v_mov_b32_e32 v2, 4.0
-; GCN-NEXT: ; implicit-def: $vgpr0
-; GCN-NEXT: .LBB0_1: ; %ComputeLoop
-; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GCN-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GCN-NEXT: v_readfirstlane_b32 s7, v1
-; GCN-NEXT: v_readlane_b32 s8, v2, s6
-; GCN-NEXT: s_mov_b32 m0, s6
-; GCN-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GCN-NEXT: v_writelane_b32 v0, s7, m0
-; GCN-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GCN-NEXT: v_add_f32_e32 v1, s8, v1
-; GCN-NEXT: s_cbranch_scc1 .LBB0_1
-; GCN-NEXT: ; %bb.2: ; %ComputeEnd
-; GCN-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GCN-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GCN-NEXT: ; implicit-def: $vgpr2
+; GCN-NEXT: s_mov_b64 s[6:7], exec
+; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GCN-NEXT: v_mbcnt_hi_u32_b32 v0, s7, v0
+; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GCN-NEXT: ; implicit-def: $vgpr1
; GCN-NEXT: s_and_saveexec_b64 s[2:3], vcc
-; GCN-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
-; GCN-NEXT: s_cbranch_execz .LBB0_6
-; GCN-NEXT: ; %bb.3:
-; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
-; GCN-NEXT: s_mov_b64 s[4:5], 0
-; GCN-NEXT: v_mov_b32_e32 v3, 0
+; GCN-NEXT: s_cbranch_execz .LBB0_4
+; GCN-NEXT: ; %bb.1:
+; GCN-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
+; GCN-NEXT: s_bcnt1_i32_b64 s1, s[6:7]
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v1, s1
+; GCN-NEXT: s_mov_b64 s[6:7], 0
+; GCN-NEXT: v_mul_f32_e32 v2, 4.0, v1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: s_load_dword s6, s[0:1], 0x0
+; GCN-NEXT: s_load_dword s0, s[4:5], 0x0
+; GCN-NEXT: v_mov_b32_e32 v3, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NEXT: v_mov_b32_e32 v2, s6
-; GCN-NEXT: .LBB0_4: ; %atomicrmw.start
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: .LBB0_2: ; %atomicrmw.start
; GCN-NEXT: ; =>This Inner Loop Header: Depth=1
-; GCN-NEXT: v_mov_b32_e32 v5, v2
-; GCN-NEXT: v_add_f32_e32 v4, v5, v1
-; GCN-NEXT: global_atomic_cmpswap v2, v3, v[4:5], s[0:1] glc
+; GCN-NEXT: v_mov_b32_e32 v5, v1
+; GCN-NEXT: v_add_f32_e32 v4, v5, v2
+; GCN-NEXT: global_atomic_cmpswap v1, v3, v[4:5], s[4:5] glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_wbinvl1
-; GCN-NEXT: v_cmp_eq_u32_e32 vcc, v2, v5
-; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GCN-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GCN-NEXT: s_cbranch_execnz .LBB0_4
-; GCN-NEXT: ; %bb.5: ; %Flow
-; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
-; GCN-NEXT: .LBB0_6: ; %Flow4
+; GCN-NEXT: v_cmp_eq_u32_e64 s[0:1], v1, v5
+; GCN-NEXT: s_or_b64 s[6:7], s[0:1], s[6:7]
+; GCN-NEXT: s_andn2_b64 exec, exec, s[6:7]
+; GCN-NEXT: s_cbranch_execnz .LBB0_2
+; GCN-NEXT: ; %bb.3: ; %Flow
+; GCN-NEXT: s_or_b64 exec, exec, s[6:7]
+; GCN-NEXT: .LBB0_4: ; %Flow2
; GCN-NEXT: s_or_b64 exec, exec, s[2:3]
-; GCN-NEXT: v_readfirstlane_b32 s0, v2
-; GCN-NEXT: v_add_f32_e32 v0, s0, v0
+; GCN-NEXT: v_readfirstlane_b32 s0, v1
+; GCN-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GCN-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NEXT: v_mad_f32 v0, v0, 4.0, s0
+; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_endpgm
%result = atomicrmw fadd ptr addrspace(1) %ptr, float 4.0 syncscope("agent") seq_cst
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
index 791862dcae8dd..d61e590123b7f 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomic_optimizer_fp_rtn.ll
@@ -7,101 +7,38 @@
; strategies are valid for only divergent values. This optimization is valid for divergent addresses. Test also covers different scopes.
define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_agent_scope_unsafe(ptr addrspace(1) inreg %ptr, float inreg %val) #0 {
-; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_address_uni_value_agent_scope_unsafe(
-; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
-; IR-ITERATIVE: 2:
-; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
-; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
-; IR-ITERATIVE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
-; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
-; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
-; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
-; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
-; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
-; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("agent") monotonic, align 4
-; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
-; IR-ITERATIVE: 12:
-; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
-; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
-; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]])
-; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = fadd float [[TMP16]], [[TMP28:%.*]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
-; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]])
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]])
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = fadd float [[ACCUMULATOR]], [[TMP24]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
-; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
-;
-; IR-DPP-LABEL: @global_atomic_fadd_uni_address_uni_value_agent_scope_unsafe(
-; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
-; IR-DPP: 2:
-; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
-; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
-; IR-DPP-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
-; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
-; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
-; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
-; IR-DPP-NEXT: [[TMP9:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-DPP-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.set.inactive.i32(i32 [[TMP9]], i32 -2147483648)
-; IR-DPP-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
-; IR-DPP-NEXT: [[TMP12:%.*]] = bitcast i32 [[TMP9]] to float
-; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP11]], i32 273, i32 15, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP14:%.*]] = fadd float [[TMP11]], [[TMP13]]
-; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP14]], i32 274, i32 15, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP16:%.*]] = fadd float [[TMP14]], [[TMP15]]
-; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP16]], i32 276, i32 15, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP18:%.*]] = fadd float [[TMP16]], [[TMP17]]
-; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP18]], i32 280, i32 15, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP20:%.*]] = fadd float [[TMP18]], [[TMP19]]
-; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP20]], i32 322, i32 10, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP22:%.*]] = fadd float [[TMP20]], [[TMP21]]
-; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP22]], i32 323, i32 12, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP24:%.*]] = fadd float [[TMP22]], [[TMP23]]
-; IR-DPP-NEXT: [[TMP25:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP24]], i32 312, i32 15, i32 15, i1 false)
-; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast float [[TMP24]] to i32
-; IR-DPP-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP26]], i32 63)
-; IR-DPP-NEXT: [[TMP28:%.*]] = bitcast i32 [[TMP27]] to float
-; IR-DPP-NEXT: [[TMP29:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP28]])
-; IR-DPP-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-DPP-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP33:%.*]]
-; IR-DPP: 31:
-; IR-DPP-NEXT: [[TMP32:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29]] syncscope("agent") monotonic, align 4
-; IR-DPP-NEXT: br label [[TMP33]]
-; IR-DPP: 33:
-; IR-DPP-NEXT: [[TMP34:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP32]], [[TMP31]] ]
-; IR-DPP-NEXT: [[TMP35:%.*]] = bitcast float [[TMP34]] to i32
-; IR-DPP-NEXT: [[TMP36:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP35]])
-; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
-; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]])
-; IR-DPP-NEXT: [[TMP39:%.*]] = fadd float [[TMP37]], [[TMP38]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-LABEL: @global_atomic_fadd_uni_address_uni_value_agent_scope_unsafe(
+; IR-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
+; IR-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
+; IR: 2:
+; IR-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
+; IR-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
+; IR-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]])
+; IR-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-NEXT: [[TMP11:%.*]] = uitofp i32 [[TMP10]] to float
+; IR-NEXT: [[TMP12:%.*]] = fmul float [[VAL:%.*]], [[TMP11]]
+; IR-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR: 14:
+; IR-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] syncscope("agent") monotonic, align 4
+; IR-NEXT: br label [[TMP16]]
+; IR: 16:
+; IR-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]])
+; IR-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-NEXT: [[TMP21:%.*]] = uitofp i32 [[TMP8]] to float
+; IR-NEXT: [[TMP22:%.*]] = fmul float [[VAL]], [[TMP21]]
+; IR-NEXT: [[TMP23:%.*]] = fadd float [[TMP20]], [[TMP22]]
+; IR-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-NEXT: br label [[TMP25]]
+; IR: 25:
+; IR-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-NEXT: ret float [[TMP26]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic, align 4
ret float %result
@@ -110,7 +47,7 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_agent_scope_uns
define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_scope_agent_scope_unsafe(ptr addrspace(1) inreg %ptr, float %val) #0 {
; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_address_div_value_scope_agent_scope_unsafe(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP19:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -121,44 +58,45 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_scope_agent_sco
; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("agent") monotonic, align 4
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP30:%.*]] syncscope("agent") monotonic, align 4
; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
; IR-ITERATIVE: 12:
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]])
; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = fadd float [[TMP16]], [[TMP28:%.*]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = fadd float [[TMP16]], [[TMP29:%.*]]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP35:%.*]], float [[TMP16]], float [[TMP17]]
+; IR-ITERATIVE-NEXT: br label [[TMP19]]
+; IR-ITERATIVE: 19:
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP18]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP20]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]])
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]])
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = fadd float [[ACCUMULATOR]], [[TMP24]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP30]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP33:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = bitcast float [[VAL:%.*]] to i32
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP23]], i32 [[TMP22]])
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[ACCUMULATOR]] to i32
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP26]], i32 [[TMP22]], i32 [[TMP27]])
+; IR-ITERATIVE-NEXT: [[TMP29]] = bitcast i32 [[TMP28]] to float
+; IR-ITERATIVE-NEXT: [[TMP30]] = fadd float [[ACCUMULATOR]], [[TMP25]]
+; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = shl i64 1, [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], -1
+; IR-ITERATIVE-NEXT: [[TMP33]] = and i64 [[ACTIVEBITS]], [[TMP32]]
+; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP35]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP35]], label [[TMP10]], label [[TMP12]]
;
; IR-DPP-LABEL: @global_atomic_fadd_uni_address_div_value_scope_agent_scope_unsafe(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP41:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -199,10 +137,11 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_scope_agent_sco
; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]])
; IR-DPP-NEXT: [[TMP39:%.*]] = fadd float [[TMP37]], [[TMP38]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP40:%.*]] = select i1 [[TMP30]], float [[TMP37]], float [[TMP39]]
+; IR-DPP-NEXT: br label [[TMP41]]
+; IR-DPP: 41:
+; IR-DPP-NEXT: [[TMP42:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP40]], [[TMP33]] ]
+; IR-DPP-NEXT: ret float [[TMP42]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic, align 4
ret float %result
@@ -211,7 +150,7 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_scope_agent_sco
define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_one_as_scope_unsafe_strictfp(ptr addrspace(1) inreg %ptr, float inreg %val) #1 {
; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_address_uni_value_one_as_scope_unsafe_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7:[0-9]+]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -219,47 +158,32 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_one_as_scope_un
; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
-; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("one-as") monotonic, align 4
-; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
-; IR-ITERATIVE: 12:
-; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
-; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
-; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
-; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
-; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP12:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL:%.*]], float [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-ITERATIVE: 14:
+; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] syncscope("one-as") monotonic, align 4
+; IR-ITERATIVE-NEXT: br label [[TMP16]]
+; IR-ITERATIVE: 16:
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP22]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-ITERATIVE-NEXT: br label [[TMP25]]
+; IR-ITERATIVE: 25:
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP26]]
;
; IR-DPP-LABEL: @global_atomic_fadd_uni_address_uni_value_one_as_scope_unsafe_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8:[0-9]+]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -267,43 +191,28 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_one_as_scope_un
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-DPP-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.set.inactive.i32(i32 [[TMP9]], i32 -2147483648) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
-; IR-DPP-NEXT: [[TMP12:%.*]] = bitcast i32 [[TMP9]] to float
-; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP11]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP11]], float [[TMP13]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP14]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP14]], float [[TMP15]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP16]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP17]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP18]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP18]], float [[TMP19]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP20]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP22]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP24:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP22]], float [[TMP23]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP25:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP24]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast float [[TMP24]] to i32
-; IR-DPP-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP26]], i32 63) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP28:%.*]] = bitcast i32 [[TMP27]] to float
-; IR-DPP-NEXT: [[TMP29:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP28]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-DPP-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP33:%.*]]
-; IR-DPP: 31:
-; IR-DPP-NEXT: [[TMP32:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29]] syncscope("one-as") monotonic, align 4
-; IR-DPP-NEXT: br label [[TMP33]]
-; IR-DPP: 33:
-; IR-DPP-NEXT: [[TMP34:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP32]], [[TMP31]] ]
-; IR-DPP-NEXT: [[TMP35:%.*]] = bitcast float [[TMP34]] to i32
-; IR-DPP-NEXT: [[TMP36:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP35]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
-; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP37]], float [[TMP38]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL:%.*]], float [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-DPP-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-DPP: 14:
+; IR-DPP-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] syncscope("one-as") monotonic, align 4
+; IR-DPP-NEXT: br label [[TMP16]]
+; IR-DPP: 16:
+; IR-DPP-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-DPP-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-DPP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP22]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-DPP-NEXT: br label [[TMP25]]
+; IR-DPP: 25:
+; IR-DPP-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-DPP-NEXT: ret float [[TMP26]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val syncscope("one-as") monotonic
ret float %result
@@ -312,7 +221,7 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_one_as_scope_un
define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_strictfp(ptr addrspace(1) inreg %ptr, float %val) #1 {
; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP19:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -323,44 +232,45 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_one_as_scope_un
; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("one-as") monotonic, align 4
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP30:%.*]] syncscope("one-as") monotonic, align 4
; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
; IR-ITERATIVE: 12:
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP29:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP35:%.*]], float [[TMP16]], float [[TMP17]]
+; IR-ITERATIVE-NEXT: br label [[TMP19]]
+; IR-ITERATIVE: 19:
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP18]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP20]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP30]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP33:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = bitcast float [[VAL:%.*]] to i32
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP23]], i32 [[TMP22]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[ACCUMULATOR]] to i32
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP26]], i32 [[TMP22]], i32 [[TMP27]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29]] = bitcast i32 [[TMP28]] to float
+; IR-ITERATIVE-NEXT: [[TMP30]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP25]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = shl i64 1, [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], -1
+; IR-ITERATIVE-NEXT: [[TMP33]] = and i64 [[ACTIVEBITS]], [[TMP32]]
+; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP35]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP35]], label [[TMP10]], label [[TMP12]]
;
; IR-DPP-LABEL: @global_atomic_fadd_uni_address_div_value_one_as_scope_unsafe_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP41:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -401,10 +311,11 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_one_as_scope_un
; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP37]], float [[TMP38]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP40:%.*]] = select i1 [[TMP30]], float [[TMP37]], float [[TMP39]]
+; IR-DPP-NEXT: br label [[TMP41]]
+; IR-DPP: 41:
+; IR-DPP-NEXT: [[TMP42:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP40]], [[TMP33]] ]
+; IR-DPP-NEXT: ret float [[TMP42]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val syncscope("one-as") monotonic
ret float %result
@@ -413,7 +324,7 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_one_as_scope_un
define amdgpu_ps float @global_atomic_fsub_uni_address_uni_value_agent_scope_strictfp(ptr addrspace(1) inreg %ptr, float inreg %val) #2 {
; IR-ITERATIVE-LABEL: @global_atomic_fsub_uni_address_uni_value_agent_scope_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -421,47 +332,32 @@ define amdgpu_ps float @global_atomic_fsub_uni_address_uni_value_agent_scope_str
; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
-; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("agent") monotonic, align 4
-; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
-; IR-ITERATIVE: 12:
-; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
-; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
-; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
-; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
-; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP12:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL:%.*]], float [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-ITERATIVE: 14:
+; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] syncscope("agent") monotonic, align 4
+; IR-ITERATIVE-NEXT: br label [[TMP16]]
+; IR-ITERATIVE: 16:
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP22]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-ITERATIVE-NEXT: br label [[TMP25]]
+; IR-ITERATIVE: 25:
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP26]]
;
; IR-DPP-LABEL: @global_atomic_fsub_uni_address_uni_value_agent_scope_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -469,43 +365,28 @@ define amdgpu_ps float @global_atomic_fsub_uni_address_uni_value_agent_scope_str
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-DPP-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.set.inactive.i32(i32 [[TMP9]], i32 -2147483648) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
-; IR-DPP-NEXT: [[TMP12:%.*]] = bitcast i32 [[TMP9]] to float
-; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP11]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP11]], float [[TMP13]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP14]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP14]], float [[TMP15]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP16]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP17]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP18]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP18]], float [[TMP19]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP20]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP22]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP24:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP22]], float [[TMP23]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP25:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP24]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast float [[TMP24]] to i32
-; IR-DPP-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP26]], i32 63) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP28:%.*]] = bitcast i32 [[TMP27]] to float
-; IR-DPP-NEXT: [[TMP29:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP28]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-DPP-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP33:%.*]]
-; IR-DPP: 31:
-; IR-DPP-NEXT: [[TMP32:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29]] syncscope("agent") monotonic, align 4
-; IR-DPP-NEXT: br label [[TMP33]]
-; IR-DPP: 33:
-; IR-DPP-NEXT: [[TMP34:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP32]], [[TMP31]] ]
-; IR-DPP-NEXT: [[TMP35:%.*]] = bitcast float [[TMP34]] to i32
-; IR-DPP-NEXT: [[TMP36:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP35]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
-; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP37]], float [[TMP38]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL:%.*]], float [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-DPP-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-DPP: 14:
+; IR-DPP-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] syncscope("agent") monotonic, align 4
+; IR-DPP-NEXT: br label [[TMP16]]
+; IR-DPP: 16:
+; IR-DPP-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-DPP-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-DPP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP22]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-DPP-NEXT: br label [[TMP25]]
+; IR-DPP: 25:
+; IR-DPP-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-DPP-NEXT: ret float [[TMP26]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic
ret float %result
@@ -514,7 +395,7 @@ define amdgpu_ps float @global_atomic_fsub_uni_address_uni_value_agent_scope_str
define amdgpu_ps float @global_atomic_fsub_uni_address_div_value_agent_scope_strictfp(ptr addrspace(1) inreg %ptr, float %val) #2 {
; IR-ITERATIVE-LABEL: @global_atomic_fsub_uni_address_div_value_agent_scope_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP19:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -525,44 +406,45 @@ define amdgpu_ps float @global_atomic_fsub_uni_address_div_value_agent_scope_str
; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fsub ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("agent") monotonic, align 4
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fsub ptr addrspace(1) [[PTR:%.*]], float [[TMP30:%.*]] syncscope("agent") monotonic, align 4
; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
; IR-ITERATIVE: 12:
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float [[TMP16]], float [[TMP29:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP35:%.*]], float [[TMP16]], float [[TMP17]]
+; IR-ITERATIVE-NEXT: br label [[TMP19]]
+; IR-ITERATIVE: 19:
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP18]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP20]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP30]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP33:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = bitcast float [[VAL:%.*]] to i32
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP23]], i32 [[TMP22]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[ACCUMULATOR]] to i32
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP26]], i32 [[TMP22]], i32 [[TMP27]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29]] = bitcast i32 [[TMP28]] to float
+; IR-ITERATIVE-NEXT: [[TMP30]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP25]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = shl i64 1, [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], -1
+; IR-ITERATIVE-NEXT: [[TMP33]] = and i64 [[ACTIVEBITS]], [[TMP32]]
+; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP35]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP35]], label [[TMP10]], label [[TMP12]]
;
; IR-DPP-LABEL: @global_atomic_fsub_uni_address_div_value_agent_scope_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP41:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -603,10 +485,11 @@ define amdgpu_ps float @global_atomic_fsub_uni_address_div_value_agent_scope_str
; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.fsub.f32(float [[TMP37]], float [[TMP38]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP40:%.*]] = select i1 [[TMP30]], float [[TMP37]], float [[TMP39]]
+; IR-DPP-NEXT: br label [[TMP41]]
+; IR-DPP: 41:
+; IR-DPP-NEXT: [[TMP42:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP40]], [[TMP33]] ]
+; IR-DPP-NEXT: ret float [[TMP42]]
;
%result = atomicrmw fsub ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic
ret float %result
@@ -615,7 +498,7 @@ define amdgpu_ps float @global_atomic_fsub_uni_address_div_value_agent_scope_str
define amdgpu_ps float @global_atomic_fmin_uni_address_uni_value_agent_scope_unsafe(ptr addrspace(1) inreg %ptr, float inreg %val) #0 {
; IR-LABEL: @global_atomic_fmin_uni_address_uni_value_agent_scope_unsafe(
; IR-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP20:%.*]]
+; IR-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP21:%.*]]
; IR: 2:
; IR-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -636,10 +519,11 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_uni_value_agent_scope_uns
; IR-NEXT: [[TMP17:%.*]] = uitofp i32 [[TMP8]] to float
; IR-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], float 0x7FF8000000000000, float [[VAL]]
; IR-NEXT: [[TMP19:%.*]] = call float @llvm.minnum.f32(float [[TMP16]], float [[TMP18]])
-; IR-NEXT: br label [[TMP20]]
-; IR: 20:
-; IR-NEXT: [[TMP21:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP19]], [[TMP12]] ]
-; IR-NEXT: ret float [[TMP21]]
+; IR-NEXT: [[TMP20:%.*]] = select i1 [[TMP9]], float [[TMP16]], float [[TMP19]]
+; IR-NEXT: br label [[TMP21]]
+; IR: 21:
+; IR-NEXT: [[TMP22:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP20]], [[TMP12]] ]
+; IR-NEXT: ret float [[TMP22]]
;
%result = atomicrmw fmin ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic
ret float %result
@@ -648,7 +532,7 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_uni_value_agent_scope_uns
define amdgpu_ps float @global_atomic_fmin_uni_address_div_value_agent_scope_unsafe(ptr addrspace(1) inreg %ptr, float %val) #0 {
; IR-ITERATIVE-LABEL: @global_atomic_fmin_uni_address_div_value_agent_scope_unsafe(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP19:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -659,44 +543,45 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_div_value_agent_scope_uns
; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fmin ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("agent") monotonic, align 4
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fmin ptr addrspace(1) [[PTR:%.*]], float [[TMP30:%.*]] syncscope("agent") monotonic, align 4
; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
; IR-ITERATIVE: 12:
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]])
; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.minnum.f32(float [[TMP16]], float [[TMP28:%.*]])
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.minnum.f32(float [[TMP16]], float [[TMP29:%.*]])
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP35:%.*]], float [[TMP16]], float [[TMP17]]
+; IR-ITERATIVE-NEXT: br label [[TMP19]]
+; IR-ITERATIVE: 19:
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP18]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP20]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]])
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]])
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.minnum.f32(float [[ACCUMULATOR]], float [[TMP24]])
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP30]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP33:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true)
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = bitcast float [[VAL:%.*]] to i32
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP23]], i32 [[TMP22]])
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[ACCUMULATOR]] to i32
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP26]], i32 [[TMP22]], i32 [[TMP27]])
+; IR-ITERATIVE-NEXT: [[TMP29]] = bitcast i32 [[TMP28]] to float
+; IR-ITERATIVE-NEXT: [[TMP30]] = call float @llvm.minnum.f32(float [[ACCUMULATOR]], float [[TMP25]])
+; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = shl i64 1, [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], -1
+; IR-ITERATIVE-NEXT: [[TMP33]] = and i64 [[ACTIVEBITS]], [[TMP32]]
+; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP35]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP35]], label [[TMP10]], label [[TMP12]]
;
; IR-DPP-LABEL: @global_atomic_fmin_uni_address_div_value_agent_scope_unsafe(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP41:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -737,10 +622,11 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_div_value_agent_scope_uns
; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]])
; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.minnum.f32(float [[TMP37]], float [[TMP38]])
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP40:%.*]] = select i1 [[TMP30]], float [[TMP37]], float [[TMP39]]
+; IR-DPP-NEXT: br label [[TMP41]]
+; IR-DPP: 41:
+; IR-DPP-NEXT: [[TMP42:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP40]], [[TMP33]] ]
+; IR-DPP-NEXT: ret float [[TMP42]]
;
%result = atomicrmw fmin ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic
ret float %result
@@ -749,7 +635,7 @@ define amdgpu_ps float @global_atomic_fmin_uni_address_div_value_agent_scope_uns
define amdgpu_ps float @global_atomic_fmax_uni_address_uni_value_agent_scope_unsafe_strictfp(ptr addrspace(1) inreg %ptr, float inreg %val) #1{
; IR-ITERATIVE-LABEL: @global_atomic_fmax_uni_address_uni_value_agent_scope_unsafe_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP20:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP21:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -770,14 +656,15 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_uni_value_agent_scope_uns
; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], float 0x7FF8000000000000, float [[VAL]]
; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP16]], float [[TMP18]], metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP20]]
-; IR-ITERATIVE: 20:
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP19]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = select i1 [[TMP9]], float [[TMP16]], float [[TMP19]]
+; IR-ITERATIVE-NEXT: br label [[TMP21]]
+; IR-ITERATIVE: 21:
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP20]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP22]]
;
; IR-DPP-LABEL: @global_atomic_fmax_uni_address_uni_value_agent_scope_unsafe_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP20:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP21:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -798,10 +685,11 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_uni_value_agent_scope_uns
; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
; IR-DPP-NEXT: [[TMP18:%.*]] = select i1 [[TMP9]], float 0x7FF8000000000000, float [[VAL]]
; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP16]], float [[TMP18]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP20]]
-; IR-DPP: 20:
-; IR-DPP-NEXT: [[TMP21:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP19]], [[TMP12]] ]
-; IR-DPP-NEXT: ret float [[TMP21]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = select i1 [[TMP9]], float [[TMP16]], float [[TMP19]]
+; IR-DPP-NEXT: br label [[TMP21]]
+; IR-DPP: 21:
+; IR-DPP-NEXT: [[TMP22:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP20]], [[TMP12]] ]
+; IR-DPP-NEXT: ret float [[TMP22]]
;
%result = atomicrmw fmax ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic
ret float %result
@@ -810,7 +698,7 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_uni_value_agent_scope_uns
define amdgpu_ps float @global_atomic_fmax_uni_address_div_value_agent_scope_unsafe_strictfp(ptr addrspace(1) inreg %ptr, float %val) #1{
; IR-ITERATIVE-LABEL: @global_atomic_fmax_uni_address_div_value_agent_scope_unsafe_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP19:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -821,44 +709,45 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_div_value_agent_scope_uns
; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fmax ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] syncscope("agent") monotonic, align 4
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fmax ptr addrspace(1) [[PTR:%.*]], float [[TMP30:%.*]] syncscope("agent") monotonic, align 4
; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
; IR-ITERATIVE: 12:
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP16]], float [[TMP29:%.*]], metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP35:%.*]], float [[TMP16]], float [[TMP17]]
+; IR-ITERATIVE-NEXT: br label [[TMP19]]
+; IR-ITERATIVE: 19:
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP18]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP20]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.maxnum.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ 0x7FF8000000000000, [[TMP2]] ], [ [[TMP30]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP33:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = bitcast float [[VAL:%.*]] to i32
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP23]], i32 [[TMP22]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[ACCUMULATOR]] to i32
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP26]], i32 [[TMP22]], i32 [[TMP27]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29]] = bitcast i32 [[TMP28]] to float
+; IR-ITERATIVE-NEXT: [[TMP30]] = call float @llvm.experimental.constrained.maxnum.f32(float [[ACCUMULATOR]], float [[TMP25]], metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = shl i64 1, [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], -1
+; IR-ITERATIVE-NEXT: [[TMP33]] = and i64 [[ACTIVEBITS]], [[TMP32]]
+; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP35]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP35]], label [[TMP10]], label [[TMP12]]
;
; IR-DPP-LABEL: @global_atomic_fmax_uni_address_div_value_agent_scope_unsafe_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP41:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -899,10 +788,11 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_div_value_agent_scope_uns
; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.maxnum.f32(float [[TMP37]], float [[TMP38]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP40:%.*]] = select i1 [[TMP30]], float [[TMP37]], float [[TMP39]]
+; IR-DPP-NEXT: br label [[TMP41]]
+; IR-DPP: 41:
+; IR-DPP-NEXT: [[TMP42:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP40]], [[TMP33]] ]
+; IR-DPP-NEXT: ret float [[TMP42]]
;
%result = atomicrmw fmax ptr addrspace(1) %ptr, float %val syncscope("agent") monotonic
ret float %result
@@ -911,7 +801,7 @@ define amdgpu_ps float @global_atomic_fmax_uni_address_div_value_agent_scope_uns
define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_system_scope_strictfp(ptr addrspace(1) inreg %ptr, float inreg %val) #2 {
; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_address_uni_value_system_scope_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -919,47 +809,32 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_system_scope_st
; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
-; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] monotonic, align 4
-; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
-; IR-ITERATIVE: 12:
-; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
-; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
-; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
-; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
-; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP12:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL:%.*]], float [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-ITERATIVE: 14:
+; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] monotonic, align 4
+; IR-ITERATIVE-NEXT: br label [[TMP16]]
+; IR-ITERATIVE: 16:
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP22]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-ITERATIVE-NEXT: br label [[TMP25]]
+; IR-ITERATIVE: 25:
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP26]]
;
; IR-DPP-LABEL: @global_atomic_fadd_uni_address_uni_value_system_scope_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP25:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -967,43 +842,28 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_system_scope_st
; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP9:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-DPP-NEXT: [[TMP10:%.*]] = call i32 @llvm.amdgcn.set.inactive.i32(i32 [[TMP9]], i32 -2147483648) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP11:%.*]] = bitcast i32 [[TMP10]] to float
-; IR-DPP-NEXT: [[TMP12:%.*]] = bitcast i32 [[TMP9]] to float
-; IR-DPP-NEXT: [[TMP13:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP11]], i32 273, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP14:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP11]], float [[TMP13]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP15:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP14]], i32 274, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP16:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP14]], float [[TMP15]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP17:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP16]], i32 276, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP18:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP17]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP19:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP18]], i32 280, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP20:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP18]], float [[TMP19]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP20]], i32 322, i32 10, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP22]], i32 323, i32 12, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP24:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP22]], float [[TMP23]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP25:%.*]] = call float @llvm.amdgcn.update.dpp.f32(float -0.000000e+00, float [[TMP24]], i32 312, i32 15, i32 15, i1 false) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast float [[TMP24]] to i32
-; IR-DPP-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP26]], i32 63) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP28:%.*]] = bitcast i32 [[TMP27]] to float
-; IR-DPP-NEXT: [[TMP29:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP28]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP30:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-DPP-NEXT: br i1 [[TMP30]], label [[TMP31:%.*]], label [[TMP33:%.*]]
-; IR-DPP: 31:
-; IR-DPP-NEXT: [[TMP32:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29]] monotonic, align 4
-; IR-DPP-NEXT: br label [[TMP33]]
-; IR-DPP: 33:
-; IR-DPP-NEXT: [[TMP34:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP32]], [[TMP31]] ]
-; IR-DPP-NEXT: [[TMP35:%.*]] = bitcast float [[TMP34]] to i32
-; IR-DPP-NEXT: [[TMP36:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP35]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
-; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
-; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP37]], float [[TMP38]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-DPP-NEXT: [[TMP11:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL:%.*]], float [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-DPP-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-DPP: 14:
+; IR-DPP-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP12]] monotonic, align 4
+; IR-DPP-NEXT: br label [[TMP16]]
+; IR-DPP: 16:
+; IR-DPP-NEXT: [[TMP17:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-DPP-NEXT: [[TMP18:%.*]] = bitcast float [[TMP17]] to i32
+; IR-DPP-NEXT: [[TMP19:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP18]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP20:%.*]] = bitcast i32 [[TMP19]] to float
+; IR-DPP-NEXT: [[TMP21:%.*]] = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP22:%.*]] = call float @llvm.experimental.constrained.fmul.f32(float [[VAL]], float [[TMP21]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP23:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP20]], float [[TMP22]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP24:%.*]] = select i1 [[TMP13]], float [[TMP20]], float [[TMP23]]
+; IR-DPP-NEXT: br label [[TMP25]]
+; IR-DPP: 25:
+; IR-DPP-NEXT: [[TMP26:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP24]], [[TMP16]] ]
+; IR-DPP-NEXT: ret float [[TMP26]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val monotonic, align 4
ret float %result
@@ -1012,7 +872,7 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_uni_value_system_scope_st
define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_system_scope_strictfp(ptr addrspace(1) inreg %ptr, float %val) #2 {
; IR-ITERATIVE-LABEL: @global_atomic_fadd_uni_address_div_value_system_scope_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP18:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP19:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -1023,44 +883,45 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_system_scope_st
; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: br label [[COMPUTELOOP:%.*]]
; IR-ITERATIVE: 10:
-; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP29:%.*]] monotonic, align 4
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], float [[TMP30:%.*]] monotonic, align 4
; IR-ITERATIVE-NEXT: br label [[TMP12:%.*]]
; IR-ITERATIVE: 12:
; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = phi float [ poison, [[COMPUTEEND:%.*]] ], [ [[TMP11]], [[TMP10:%.*]] ]
; IR-ITERATIVE-NEXT: [[TMP14:%.*]] = bitcast float [[TMP13]] to i32
; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP14]]) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP16:%.*]] = bitcast i32 [[TMP15]] to float
-; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP28:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP18]]
-; IR-ITERATIVE: 18:
-; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP17]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret float [[TMP19]]
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP16]], float [[TMP29:%.*]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = select i1 [[TMP35:%.*]], float [[TMP16]], float [[TMP17]]
+; IR-ITERATIVE-NEXT: br label [[TMP19]]
+; IR-ITERATIVE: 19:
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP18]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret float [[TMP20]]
; IR-ITERATIVE: ComputeLoop:
-; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP28]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP32:%.*]], [[COMPUTELOOP]] ]
-; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
-; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = bitcast float [[VAL:%.*]] to i32
-; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP22]], i32 [[TMP21]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = bitcast i32 [[TMP23]] to float
-; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast float [[ACCUMULATOR]] to i32
-; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP25]], i32 [[TMP21]], i32 [[TMP26]]) #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP28]] = bitcast i32 [[TMP27]] to float
-; IR-ITERATIVE-NEXT: [[TMP29]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP24]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = shl i64 1, [[TMP20]]
-; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = xor i64 [[TMP30]], -1
-; IR-ITERATIVE-NEXT: [[TMP32]] = and i64 [[ACTIVEBITS]], [[TMP31]]
-; IR-ITERATIVE-NEXT: [[TMP33:%.*]] = icmp eq i64 [[TMP32]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP33]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
+; IR-ITERATIVE-NEXT: [[ACCUMULATOR:%.*]] = phi float [ -0.000000e+00, [[TMP2]] ], [ [[TMP30]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[OLDVALUEPHI:%.*]] = phi float [ poison, [[TMP2]] ], [ [[TMP29]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[ACTIVEBITS:%.*]] = phi i64 [ [[TMP9]], [[TMP2]] ], [ [[TMP33:%.*]], [[COMPUTELOOP]] ]
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = call i64 @llvm.cttz.i64(i64 [[ACTIVEBITS]], i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = trunc i64 [[TMP21]] to i32
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = bitcast float [[VAL:%.*]] to i32
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = call i32 @llvm.amdgcn.readlane.i32(i32 [[TMP23]], i32 [[TMP22]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = bitcast i32 [[TMP24]] to float
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast float [[ACCUMULATOR]] to i32
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = bitcast float [[OLDVALUEPHI]] to i32
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call i32 @llvm.amdgcn.writelane.i32(i32 [[TMP26]], i32 [[TMP22]], i32 [[TMP27]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29]] = bitcast i32 [[TMP28]] to float
+; IR-ITERATIVE-NEXT: [[TMP30]] = call float @llvm.experimental.constrained.fadd.f32(float [[ACCUMULATOR]], float [[TMP25]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP31:%.*]] = shl i64 1, [[TMP21]]
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], -1
+; IR-ITERATIVE-NEXT: [[TMP33]] = and i64 [[ACTIVEBITS]], [[TMP32]]
+; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[COMPUTEEND]], label [[COMPUTELOOP]]
; IR-ITERATIVE: ComputeEnd:
-; IR-ITERATIVE-NEXT: [[TMP34:%.*]] = icmp eq i32 [[TMP8]], 0
-; IR-ITERATIVE-NEXT: br i1 [[TMP34]], label [[TMP10]], label [[TMP12]]
+; IR-ITERATIVE-NEXT: [[TMP35]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP35]], label [[TMP10]], label [[TMP12]]
;
; IR-DPP-LABEL: @global_atomic_fadd_uni_address_div_value_system_scope_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP40:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP41:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -1101,10 +962,11 @@ define amdgpu_ps float @global_atomic_fadd_uni_address_div_value_system_scope_st
; IR-DPP-NEXT: [[TMP37:%.*]] = bitcast i32 [[TMP36]] to float
; IR-DPP-NEXT: [[TMP38:%.*]] = call float @llvm.amdgcn.strict.wwm.f32(float [[TMP25]]) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP39:%.*]] = call float @llvm.experimental.constrained.fadd.f32(float [[TMP37]], float [[TMP38]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP40]]
-; IR-DPP: 40:
-; IR-DPP-NEXT: [[TMP41:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP39]], [[TMP33]] ]
-; IR-DPP-NEXT: ret float [[TMP41]]
+; IR-DPP-NEXT: [[TMP40:%.*]] = select i1 [[TMP30]], float [[TMP37]], float [[TMP39]]
+; IR-DPP-NEXT: br label [[TMP41]]
+; IR-DPP: 41:
+; IR-DPP-NEXT: [[TMP42:%.*]] = phi float [ poison, [[TMP0:%.*]] ], [ [[TMP40]], [[TMP33]] ]
+; IR-DPP-NEXT: ret float [[TMP42]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, float %val monotonic, align 4
ret float %result
@@ -1220,8 +1082,43 @@ define amdgpu_ps float @global_atomic_fadd_div_address_div_value_system_scope_st
define amdgpu_ps double @global_atomic_fadd_double_uni_address_uni_value_agent_scope_unsafe(ptr addrspace(1) inreg %ptr, double inreg %val) #0 {
; IR-LABEL: @global_atomic_fadd_double_uni_address_uni_value_agent_scope_unsafe(
-; IR-NEXT: [[RESULT:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VAL:%.*]] syncscope("agent") monotonic, align 4
-; IR-NEXT: ret double [[RESULT]]
+; IR-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
+; IR-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR: 2:
+; IR-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
+; IR-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0)
+; IR-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]])
+; IR-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]])
+; IR-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-NEXT: [[TMP11:%.*]] = uitofp i32 [[TMP10]] to double
+; IR-NEXT: [[TMP12:%.*]] = fmul double [[VAL:%.*]], [[TMP11]]
+; IR-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR: 14:
+; IR-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] syncscope("agent") monotonic, align 4
+; IR-NEXT: br label [[TMP16]]
+; IR: 16:
+; IR-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]])
+; IR-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]])
+; IR-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-NEXT: [[TMP27:%.*]] = uitofp i32 [[TMP8]] to double
+; IR-NEXT: [[TMP28:%.*]] = fmul double [[VAL]], [[TMP27]]
+; IR-NEXT: [[TMP29:%.*]] = fadd double [[TMP26]], [[TMP28]]
+; IR-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-NEXT: br label [[TMP31]]
+; IR: 31:
+; IR-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-NEXT: ret double [[TMP32]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, double %val syncscope("agent") monotonic, align 4
ret double %result
@@ -1237,9 +1134,83 @@ define amdgpu_ps double @global_atomic_fadd_double_uni_address_div_value_scope_a
}
define amdgpu_ps double @global_atomic_fadd_double_uni_address_uni_value_one_as_scope_unsafe_strictfp(ptr addrspace(1) inreg %ptr, double inreg %val) #1 {
-; IR-LABEL: @global_atomic_fadd_double_uni_address_uni_value_one_as_scope_unsafe_strictfp(
-; IR-NEXT: [[RESULT:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VAL:%.*]] syncscope("one-as") monotonic, align 8
-; IR-NEXT: ret double [[RESULT]]
+; IR-ITERATIVE-LABEL: @global_atomic_fadd_double_uni_address_uni_value_one_as_scope_unsafe_strictfp(
+; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR-ITERATIVE: 2:
+; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-ITERATIVE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP12:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL:%.*]], double [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-ITERATIVE: 14:
+; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] syncscope("one-as") monotonic, align 8
+; IR-ITERATIVE-NEXT: br label [[TMP16]]
+; IR-ITERATIVE: 16:
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL]], double [[TMP27]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP26]], double [[TMP28]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-ITERATIVE-NEXT: br label [[TMP31]]
+; IR-ITERATIVE: 31:
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-ITERATIVE-NEXT: ret double [[TMP32]]
+;
+; IR-DPP-LABEL: @global_atomic_fadd_double_uni_address_uni_value_one_as_scope_unsafe_strictfp(
+; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR-DPP: 2:
+; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-DPP-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL:%.*]], double [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-DPP-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-DPP: 14:
+; IR-DPP-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] syncscope("one-as") monotonic, align 8
+; IR-DPP-NEXT: br label [[TMP16]]
+; IR-DPP: 16:
+; IR-DPP-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-DPP-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-DPP-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-DPP-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-DPP-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-DPP-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-DPP-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-DPP-NEXT: [[TMP27:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP28:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL]], double [[TMP27]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP29:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP26]], double [[TMP28]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-DPP-NEXT: br label [[TMP31]]
+; IR-DPP: 31:
+; IR-DPP-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-DPP-NEXT: ret double [[TMP32]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, double %val syncscope("one-as") monotonic
ret double %result
@@ -1255,9 +1226,83 @@ define amdgpu_ps double @global_atomic_fadd_double_uni_address_div_value_one_as_
}
define amdgpu_ps double @global_atomic_fsub_double_uni_address_uni_value_agent_scope_strictfp(ptr addrspace(1) inreg %ptr, double inreg %val) #2 {
-; IR-LABEL: @global_atomic_fsub_double_uni_address_uni_value_agent_scope_strictfp(
-; IR-NEXT: [[RESULT:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VAL:%.*]] syncscope("agent") monotonic, align 8
-; IR-NEXT: ret double [[RESULT]]
+; IR-ITERATIVE-LABEL: @global_atomic_fsub_double_uni_address_uni_value_agent_scope_strictfp(
+; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR-ITERATIVE: 2:
+; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-ITERATIVE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP12:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL:%.*]], double [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-ITERATIVE: 14:
+; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] syncscope("agent") monotonic, align 8
+; IR-ITERATIVE-NEXT: br label [[TMP16]]
+; IR-ITERATIVE: 16:
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL]], double [[TMP27]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP26]], double [[TMP28]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-ITERATIVE-NEXT: br label [[TMP31]]
+; IR-ITERATIVE: 31:
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-ITERATIVE-NEXT: ret double [[TMP32]]
+;
+; IR-DPP-LABEL: @global_atomic_fsub_double_uni_address_uni_value_agent_scope_strictfp(
+; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR-DPP: 2:
+; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-DPP-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL:%.*]], double [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-DPP-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-DPP: 14:
+; IR-DPP-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] syncscope("agent") monotonic, align 8
+; IR-DPP-NEXT: br label [[TMP16]]
+; IR-DPP: 16:
+; IR-DPP-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-DPP-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-DPP-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-DPP-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-DPP-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-DPP-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-DPP-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-DPP-NEXT: [[TMP27:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP28:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL]], double [[TMP27]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP29:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP26]], double [[TMP28]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-DPP-NEXT: br label [[TMP31]]
+; IR-DPP: 31:
+; IR-DPP-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-DPP-NEXT: ret double [[TMP32]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, double %val syncscope("agent") monotonic
ret double %result
@@ -1275,7 +1320,7 @@ define amdgpu_ps double @global_atomic_fsub_double_uni_address_div_value_agent_s
define amdgpu_ps double @global_atomic_fmin_double_uni_address_uni_value_agent_scope_unsafe(ptr addrspace(1) inreg %ptr, double inreg %val) #0 {
; IR-LABEL: @global_atomic_fmin_double_uni_address_uni_value_agent_scope_unsafe(
; IR-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live()
-; IR-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP26:%.*]]
+; IR-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP27:%.*]]
; IR: 2:
; IR-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true)
; IR-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -1302,10 +1347,11 @@ define amdgpu_ps double @global_atomic_fmin_double_uni_address_uni_value_agent_s
; IR-NEXT: [[TMP23:%.*]] = uitofp i32 [[TMP8]] to double
; IR-NEXT: [[TMP24:%.*]] = select i1 [[TMP9]], double 0x7FF8000000000000, double [[VAL]]
; IR-NEXT: [[TMP25:%.*]] = call double @llvm.minnum.f64(double [[TMP22]], double [[TMP24]])
-; IR-NEXT: br label [[TMP26]]
-; IR: 26:
-; IR-NEXT: [[TMP27:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP25]], [[TMP12]] ]
-; IR-NEXT: ret double [[TMP27]]
+; IR-NEXT: [[TMP26:%.*]] = select i1 [[TMP9]], double [[TMP22]], double [[TMP25]]
+; IR-NEXT: br label [[TMP27]]
+; IR: 27:
+; IR-NEXT: [[TMP28:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP26]], [[TMP12]] ]
+; IR-NEXT: ret double [[TMP28]]
;
%result = atomicrmw fmin ptr addrspace(1) %ptr, double %val syncscope("agent") monotonic
ret double %result
@@ -1323,7 +1369,7 @@ define amdgpu_ps double @global_atomic_fmin_double_uni_address_div_value_agent_s
define amdgpu_ps double @global_atomic__fmax_double_uni_address_uni_value_agent_scope_unsafe_strictfp(ptr addrspace(1) inreg %ptr, double inreg %val) #1{
; IR-ITERATIVE-LABEL: @global_atomic__fmax_double_uni_address_uni_value_agent_scope_unsafe_strictfp(
; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP26:%.*]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP27:%.*]]
; IR-ITERATIVE: 2:
; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -1350,14 +1396,15 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_uni_value_agent_
; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = select i1 [[TMP9]], double 0x7FF8000000000000, double [[VAL]]
; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP22]], double [[TMP24]], metadata !"fpexcept.strict") #[[ATTR7]]
-; IR-ITERATIVE-NEXT: br label [[TMP26]]
-; IR-ITERATIVE: 26:
-; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP25]], [[TMP12]] ]
-; IR-ITERATIVE-NEXT: ret double [[TMP27]]
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = select i1 [[TMP9]], double [[TMP22]], double [[TMP25]]
+; IR-ITERATIVE-NEXT: br label [[TMP27]]
+; IR-ITERATIVE: 27:
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP26]], [[TMP12]] ]
+; IR-ITERATIVE-NEXT: ret double [[TMP28]]
;
; IR-DPP-LABEL: @global_atomic__fmax_double_uni_address_uni_value_agent_scope_unsafe_strictfp(
; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
-; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP26:%.*]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP27:%.*]]
; IR-DPP: 2:
; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
@@ -1384,10 +1431,11 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_uni_value_agent_
; IR-DPP-NEXT: [[TMP23:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
; IR-DPP-NEXT: [[TMP24:%.*]] = select i1 [[TMP9]], double 0x7FF8000000000000, double [[VAL]]
; IR-DPP-NEXT: [[TMP25:%.*]] = call double @llvm.experimental.constrained.maxnum.f64(double [[TMP22]], double [[TMP24]], metadata !"fpexcept.strict") #[[ATTR8]]
-; IR-DPP-NEXT: br label [[TMP26]]
-; IR-DPP: 26:
-; IR-DPP-NEXT: [[TMP27:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP25]], [[TMP12]] ]
-; IR-DPP-NEXT: ret double [[TMP27]]
+; IR-DPP-NEXT: [[TMP26:%.*]] = select i1 [[TMP9]], double [[TMP22]], double [[TMP25]]
+; IR-DPP-NEXT: br label [[TMP27]]
+; IR-DPP: 27:
+; IR-DPP-NEXT: [[TMP28:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP26]], [[TMP12]] ]
+; IR-DPP-NEXT: ret double [[TMP28]]
;
%result = atomicrmw fmax ptr addrspace(1) %ptr, double %val syncscope("agent") monotonic
ret double %result
@@ -1403,9 +1451,83 @@ define amdgpu_ps double @global_atomic__fmax_double_uni_address_div_value_agent_
}
define amdgpu_ps double @global_atomic_fadd_double_uni_address_uni_value_system_scope_strictfp(ptr addrspace(1) inreg %ptr, double inreg %val) #2 {
-; IR-LABEL: @global_atomic_fadd_double_uni_address_uni_value_system_scope_strictfp(
-; IR-NEXT: [[RESULT:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[VAL:%.*]] monotonic, align 4
-; IR-NEXT: ret double [[RESULT]]
+; IR-ITERATIVE-LABEL: @global_atomic_fadd_double_uni_address_uni_value_system_scope_strictfp(
+; IR-ITERATIVE-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR7]]
+; IR-ITERATIVE-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR-ITERATIVE: 2:
+; IR-ITERATIVE-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-ITERATIVE-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-ITERATIVE-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-ITERATIVE-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-ITERATIVE-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP12:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL:%.*]], double [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-ITERATIVE-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-ITERATIVE: 14:
+; IR-ITERATIVE-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] monotonic, align 4
+; IR-ITERATIVE-NEXT: br label [[TMP16]]
+; IR-ITERATIVE: 16:
+; IR-ITERATIVE-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-ITERATIVE-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-ITERATIVE-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-ITERATIVE-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-ITERATIVE-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-ITERATIVE-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]]) #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-ITERATIVE-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-ITERATIVE-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-ITERATIVE-NEXT: [[TMP27:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP28:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL]], double [[TMP27]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP29:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP26]], double [[TMP28]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR7]]
+; IR-ITERATIVE-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-ITERATIVE-NEXT: br label [[TMP31]]
+; IR-ITERATIVE: 31:
+; IR-ITERATIVE-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-ITERATIVE-NEXT: ret double [[TMP32]]
+;
+; IR-DPP-LABEL: @global_atomic_fadd_double_uni_address_uni_value_system_scope_strictfp(
+; IR-DPP-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.ps.live() #[[ATTR8]]
+; IR-DPP-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP31:%.*]]
+; IR-DPP: 2:
+; IR-DPP-NEXT: [[TMP3:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 true) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP3]] to i32
+; IR-DPP-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP3]], 32
+; IR-DPP-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP5]] to i32
+; IR-DPP-NEXT: [[TMP7:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 [[TMP4]], i32 0) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP8:%.*]] = call i32 @llvm.amdgcn.mbcnt.hi(i32 [[TMP6]], i32 [[TMP7]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP9:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP3]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i32
+; IR-DPP-NEXT: [[TMP11:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP10]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP12:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL:%.*]], double [[TMP11]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP13:%.*]] = icmp eq i32 [[TMP8]], 0
+; IR-DPP-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP16:%.*]]
+; IR-DPP: 14:
+; IR-DPP-NEXT: [[TMP15:%.*]] = atomicrmw fadd ptr addrspace(1) [[PTR:%.*]], double [[TMP12]] monotonic, align 4
+; IR-DPP-NEXT: br label [[TMP16]]
+; IR-DPP: 16:
+; IR-DPP-NEXT: [[TMP17:%.*]] = phi double [ poison, [[TMP2]] ], [ [[TMP15]], [[TMP14]] ]
+; IR-DPP-NEXT: [[TMP18:%.*]] = bitcast double [[TMP17]] to i64
+; IR-DPP-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i32
+; IR-DPP-NEXT: [[TMP20:%.*]] = lshr i64 [[TMP18]], 32
+; IR-DPP-NEXT: [[TMP21:%.*]] = trunc i64 [[TMP20]] to i32
+; IR-DPP-NEXT: [[TMP22:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP19]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP23:%.*]] = call i32 @llvm.amdgcn.readfirstlane.i32(i32 [[TMP21]]) #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP24:%.*]] = insertelement <2 x i32> poison, i32 [[TMP22]], i32 0
+; IR-DPP-NEXT: [[TMP25:%.*]] = insertelement <2 x i32> [[TMP24]], i32 [[TMP23]], i32 1
+; IR-DPP-NEXT: [[TMP26:%.*]] = bitcast <2 x i32> [[TMP25]] to double
+; IR-DPP-NEXT: [[TMP27:%.*]] = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 [[TMP8]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP28:%.*]] = call double @llvm.experimental.constrained.fmul.f64(double [[VAL]], double [[TMP27]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP29:%.*]] = call double @llvm.experimental.constrained.fadd.f64(double [[TMP26]], double [[TMP28]], metadata !"round.dynamic", metadata !"fpexcept.strict") #[[ATTR8]]
+; IR-DPP-NEXT: [[TMP30:%.*]] = select i1 [[TMP13]], double [[TMP26]], double [[TMP29]]
+; IR-DPP-NEXT: br label [[TMP31]]
+; IR-DPP: 31:
+; IR-DPP-NEXT: [[TMP32:%.*]] = phi double [ poison, [[TMP0:%.*]] ], [ [[TMP30]], [[TMP16]] ]
+; IR-DPP-NEXT: ret double [[TMP32]]
;
%result = atomicrmw fadd ptr addrspace(1) %ptr, double %val monotonic, align 4
ret double %result
diff --git a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
index 9744bd42786ea..03ee6a325fbbc 100644
--- a/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/local-atomicrmw-fadd.ll
@@ -6979,95 +6979,88 @@ define void @local_atomic_fadd_noret_v2bf16__ofset(ptr addrspace(3) %ptr, <2 x b
define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3) %ptrf, i32 %idx) {
; GFX12-LABEL: local_ds_fadd:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_mov_b32_e32 v1, 0x42280000
-; GFX12-NEXT: s_mov_b32 s2, exec_lo
-; GFX12-NEXT: s_brev_b32 s4, 1
-; GFX12-NEXT: ; implicit-def: $vgpr0
-; GFX12-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_ctz_i32_b32 s3, s2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: v_readlane_b32 s5, v1, s3
-; GFX12-NEXT: s_lshl_b32 s6, 1, s3
-; GFX12-NEXT: v_writelane_b32 v0, s4, s3
-; GFX12-NEXT: s_and_not1_b32 s2, s2, s6
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_lg_u32 s2, 0
-; GFX12-NEXT: s_add_f32 s4, s4, s5
-; GFX12-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX12-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX12-NEXT: s_load_b64 s[2:3], s[0:1], 0x8
-; GFX12-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX12-NEXT: s_load_b64 s[4:5], s[0:1], 0x8
+; GFX12-NEXT: s_mov_b32 s6, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_add_co_i32 s3, s3, 4
-; GFX12-NEXT: s_and_saveexec_b32 s5, vcc_lo
-; GFX12-NEXT: s_xor_b32 s5, exec_lo, s5
-; GFX12-NEXT: s_cbranch_execz .LBB28_4
-; GFX12-NEXT: ; %bb.3:
-; GFX12-NEXT: s_lshl_b32 s6, s3, 3
+; GFX12-NEXT: s_add_co_i32 s3, s5, 4
+; GFX12-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX12-NEXT: s_cbranch_execz .LBB28_2
+; GFX12-NEXT: ; %bb.1:
+; GFX12-NEXT: s_bcnt1_i32_b32 s5, s6
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s6
-; GFX12-NEXT: ds_add_rtn_f32 v1, v1, v2
+; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s5
+; GFX12-NEXT: s_lshl_b32 s5, s3, 3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX12-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
-; GFX12-NEXT: .LBB28_4:
-; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s5
+; GFX12-NEXT: .LBB28_2:
+; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-NEXT: s_mov_b32 s6, exec_lo
+; GFX12-NEXT: s_mov_b32 s7, exec_lo
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
-; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
-; GFX12-NEXT: s_mov_b32 s4, exec_lo
+; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
+; GFX12-NEXT: s_mov_b32 s6, exec_lo
; GFX12-NEXT: v_cmpx_eq_u32_e32 0, v2
-; GFX12-NEXT: s_cbranch_execz .LBB28_6
-; GFX12-NEXT: ; %bb.5:
-; GFX12-NEXT: s_bcnt1_i32_b32 s6, s6
-; GFX12-NEXT: s_lshl_b32 s3, s3, 4
-; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX12-NEXT: s_cbranch_execz .LBB28_4
+; GFX12-NEXT: ; %bb.3:
+; GFX12-NEXT: s_bcnt1_i32_b32 s2, s7
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX12-NEXT: s_lshl_b32 s2, s3, 4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX12-NEXT: ds_add_f32 v2, v1
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
-; GFX12-NEXT: .LBB28_6:
-; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-NEXT: v_add_f32_e32 v1, s5, v0
-; GFX12-NEXT: s_mov_b32 s4, exec_lo
-; GFX12-NEXT: s_brev_b32 s3, 1
+; GFX12-NEXT: .LBB28_4:
+; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX12-NEXT: s_mov_b32 s3, exec_lo
+; GFX12-NEXT: s_brev_b32 s2, 1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX12-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_cndmask_b32_e64 v1, v0, s5, vcc_lo
; GFX12-NEXT: ; implicit-def: $vgpr0
-; GFX12-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX12-NEXT: .LBB28_5: ; %ComputeLoop
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_ctz_i32_b32 s5, s4
+; GFX12-NEXT: s_ctz_i32_b32 s5, s3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: v_readlane_b32 s6, v1, s5
; GFX12-NEXT: s_lshl_b32 s7, 1, s5
-; GFX12-NEXT: v_writelane_b32 v0, s3, s5
-; GFX12-NEXT: s_and_not1_b32 s4, s4, s7
+; GFX12-NEXT: v_writelane_b32 v0, s2, s5
+; GFX12-NEXT: s_and_not1_b32 s3, s3, s7
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_lg_u32 s4, 0
-; GFX12-NEXT: s_add_f32 s3, s3, s6
-; GFX12-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX12-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX12-NEXT: s_cmp_lg_u32 s3, 0
+; GFX12-NEXT: s_add_f32 s2, s2, s6
+; GFX12-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX12-NEXT: ; %bb.6: ; %ComputeEnd
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12-NEXT: ; implicit-def: $vgpr1
-; GFX12-NEXT: s_and_saveexec_b32 s4, vcc_lo
-; GFX12-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX12-NEXT: s_cbranch_execz .LBB28_10
-; GFX12-NEXT: ; %bb.9:
-; GFX12-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
+; GFX12-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX12-NEXT: s_xor_b32 s3, exec_lo, s3
+; GFX12-NEXT: s_cbranch_execz .LBB28_8
+; GFX12-NEXT: ; %bb.7:
+; GFX12-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s2
; GFX12-NEXT: ds_add_rtn_f32 v1, v1, v2
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: global_inv scope:SCOPE_SE
-; GFX12-NEXT: .LBB28_10:
-; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX12-NEXT: .LBB28_8:
+; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s2, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT: s_nop 0
@@ -7076,191 +7069,174 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
;
; GFX940-LABEL: local_ds_fadd:
; GFX940: ; %bb.0:
+; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX940-NEXT: s_mov_b64 s[2:3], exec
-; GFX940-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX940-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX940-NEXT: ; implicit-def: $vgpr0
-; GFX940-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX940-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX940-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX940-NEXT: v_readfirstlane_b32 s7, v1
-; GFX940-NEXT: v_readlane_b32 s8, v2, s6
-; GFX940-NEXT: s_mov_b32 m0, s6
-; GFX940-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX940-NEXT: v_writelane_b32 v0, s7, m0
-; GFX940-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX940-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX940-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX940-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX940-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX940-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX940-NEXT: ; implicit-def: $vgpr2
+; GFX940-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX940-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX940-NEXT: s_waitcnt lgkmcnt(0)
+; GFX940-NEXT: s_add_i32 s5, s5, 4
+; GFX940-NEXT: ; implicit-def: $vgpr1
+; GFX940-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX940-NEXT: s_cbranch_execz .LBB28_2
+; GFX940-NEXT: ; %bb.1:
+; GFX940-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX940-NEXT: s_lshl_b32 s8, s5, 3
+; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX940-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX940-NEXT: v_mov_b32_e32 v2, s8
+; GFX940-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-NEXT: s_add_i32 s3, s3, 4
-; GFX940-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX940-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX940-NEXT: .LBB28_2:
+; GFX940-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX940-NEXT: s_mov_b64 s[8:9], exec
+; GFX940-NEXT: v_readfirstlane_b32 s10, v1
+; GFX940-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX940-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX940-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX940-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX940-NEXT: s_cbranch_execz .LBB28_4
; GFX940-NEXT: ; %bb.3:
-; GFX940-NEXT: s_lshl_b32 s6, s3, 3
-; GFX940-NEXT: v_mov_b32_e32 v2, s6
-; GFX940-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX940-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-NEXT: .LBB28_4:
-; GFX940-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX940-NEXT: s_mov_b64 s[6:7], exec
-; GFX940-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX940-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX940-NEXT: v_readfirstlane_b32 s8, v2
-; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX940-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX940-NEXT: s_cbranch_execz .LBB28_6
-; GFX940-NEXT: ; %bb.5:
-; GFX940-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX940-NEXT: s_lshl_b32 s3, s3, 4
+; GFX940-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX940-NEXT: s_lshl_b32 s2, s5, 4
; GFX940-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX940-NEXT: v_mov_b32_e32 v2, s3
+; GFX940-NEXT: v_mov_b32_e32 v2, s2
; GFX940-NEXT: ds_add_f32 v2, v1
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-NEXT: .LBB28_6:
-; GFX940-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX940-NEXT: s_mov_b64 s[4:5], exec
-; GFX940-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX940-NEXT: .LBB28_4:
+; GFX940-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX940-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX940-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX940-NEXT: v_mov_b32_e32 v1, s10
+; GFX940-NEXT: s_mov_b64 s[2:3], exec
+; GFX940-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX940-NEXT: v_bfrev_b32_e32 v1, 1
; GFX940-NEXT: ; implicit-def: $vgpr0
-; GFX940-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX940-NEXT: .LBB28_5: ; %ComputeLoop
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX940-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX940-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX940-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX940-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX940-NEXT: v_readfirstlane_b32 s8, v1
-; GFX940-NEXT: v_readlane_b32 s9, v2, s3
-; GFX940-NEXT: s_mov_b32 m0, s3
-; GFX940-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX940-NEXT: v_readlane_b32 s9, v2, s5
+; GFX940-NEXT: s_mov_b32 m0, s5
+; GFX940-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX940-NEXT: v_writelane_b32 v0, s8, m0
-; GFX940-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX940-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX940-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX940-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX940-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX940-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX940-NEXT: ; %bb.6: ; %ComputeEnd
; GFX940-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX940-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX940-NEXT: ; implicit-def: $vgpr2
-; GFX940-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX940-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX940-NEXT: s_cbranch_execz .LBB28_10
-; GFX940-NEXT: ; %bb.9:
-; GFX940-NEXT: v_mov_b32_e32 v2, s2
+; GFX940-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX940-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX940-NEXT: s_cbranch_execz .LBB28_8
+; GFX940-NEXT: ; %bb.7:
+; GFX940-NEXT: v_mov_b32_e32 v2, s4
; GFX940-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-NEXT: .LBB28_10:
-; GFX940-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX940-NEXT: .LBB28_8:
+; GFX940-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX940-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX940-NEXT: v_readfirstlane_b32 s2, v2
; GFX940-NEXT: v_mov_b32_e32 v1, 0
; GFX940-NEXT: s_nop 0
; GFX940-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX940-NEXT: v_mov_b32_e32 v2, s2
+; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-NEXT: global_store_dword v1, v0, s[0:1] sc0 sc1
; GFX940-NEXT: s_endpgm
;
; GFX11-LABEL: local_ds_fadd:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX11-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX11-NEXT: s_mov_b32 s2, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr0
-; GFX11-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x8
+; GFX11-NEXT: s_mov_b32 s6, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_ctz_i32_b32 s3, s2
-; GFX11-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readlane_b32 s5, v2, s3
-; GFX11-NEXT: s_lshl_b32 s6, 1, s3
-; GFX11-NEXT: s_and_not1_b32 s2, s2, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_writelane_b32 v0, s4, s3
-; GFX11-NEXT: v_add_f32_e32 v1, s5, v1
-; GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX11-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x8
-; GFX11-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: ; implicit-def: $vgpr2
+; GFX11-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_add_i32 s3, s3, 4
-; GFX11-NEXT: s_and_saveexec_b32 s4, vcc_lo
-; GFX11-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX11-NEXT: s_cbranch_execz .LBB28_4
-; GFX11-NEXT: ; %bb.3:
-; GFX11-NEXT: s_lshl_b32 s5, s3, 3
+; GFX11-NEXT: s_add_i32 s3, s5, 4
+; GFX11-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX11-NEXT: s_cbranch_execz .LBB28_2
+; GFX11-NEXT: ; %bb.1:
+; GFX11-NEXT: s_bcnt1_i32_b32 s5, s6
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b32_e32 v2, s5
-; GFX11-NEXT: ds_add_rtn_f32 v2, v2, v1
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s5
+; GFX11-NEXT: s_lshl_b32 s5, s3, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX11-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: .LBB28_4:
-; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX11-NEXT: .LBB28_2:
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX11-NEXT: s_mov_b32 s7, exec_lo
+; GFX11-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
; GFX11-NEXT: s_mov_b32 s6, exec_lo
-; GFX11-NEXT: v_readfirstlane_b32 s4, v2
-; GFX11-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX11-NEXT: s_mov_b32 s5, exec_lo
-; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v1
-; GFX11-NEXT: s_cbranch_execz .LBB28_6
-; GFX11-NEXT: ; %bb.5:
-; GFX11-NEXT: s_bcnt1_i32_b32 s6, s6
-; GFX11-NEXT: s_lshl_b32 s3, s3, 4
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX11-NEXT: s_cbranch_execz .LBB28_4
+; GFX11-NEXT: ; %bb.3:
+; GFX11-NEXT: s_bcnt1_i32_b32 s2, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX11-NEXT: s_lshl_b32 s2, s3, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX11-NEXT: ds_add_f32 v2, v1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: .LBB28_6:
-; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX11-NEXT: v_add_f32_e32 v2, s4, v0
+; GFX11-NEXT: .LBB28_4:
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX11-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX11-NEXT: s_mov_b32 s3, exec_lo
+; GFX11-NEXT: s_mov_b32 s2, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX11-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v0, s5, vcc_lo
; GFX11-NEXT: ; implicit-def: $vgpr0
-; GFX11-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX11-NEXT: .LBB28_5: ; %ComputeLoop
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_ctz_i32_b32 s4, s3
+; GFX11-NEXT: s_ctz_i32_b32 s3, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s5, v1
-; GFX11-NEXT: v_readlane_b32 s6, v2, s4
-; GFX11-NEXT: s_lshl_b32 s7, 1, s4
+; GFX11-NEXT: v_readlane_b32 s6, v2, s3
+; GFX11-NEXT: s_lshl_b32 s7, 1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: s_and_not1_b32 s3, s3, s7
-; GFX11-NEXT: v_writelane_b32 v0, s5, s4
+; GFX11-NEXT: s_and_not1_b32 s2, s2, s7
+; GFX11-NEXT: v_writelane_b32 v0, s5, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v1, s6, v1
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX11-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX11-NEXT: ; %bb.6: ; %ComputeEnd
; GFX11-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: ; implicit-def: $vgpr2
-; GFX11-NEXT: s_and_saveexec_b32 s3, vcc_lo
-; GFX11-NEXT: s_xor_b32 s3, exec_lo, s3
-; GFX11-NEXT: s_cbranch_execz .LBB28_10
-; GFX11-NEXT: ; %bb.9:
-; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX11-NEXT: s_xor_b32 s2, exec_lo, s2
+; GFX11-NEXT: s_cbranch_execz .LBB28_8
+; GFX11-NEXT: ; %bb.7:
+; GFX11-NEXT: v_mov_b32_e32 v2, s4
; GFX11-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: buffer_gl0_inv
-; GFX11-NEXT: .LBB28_10:
-; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX11-NEXT: .LBB28_8:
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s2, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_nop 0
@@ -7269,368 +7245,335 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
;
; GFX10-LABEL: local_ds_fadd:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX10-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX10-NEXT: s_mov_b32 s2, exec_lo
-; GFX10-NEXT: ; implicit-def: $vgpr0
-; GFX10-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_ff1_i32_b32 s3, s2
-; GFX10-NEXT: v_readfirstlane_b32 s4, v1
-; GFX10-NEXT: v_readlane_b32 s5, v2, s3
-; GFX10-NEXT: s_lshl_b32 s6, 1, s3
-; GFX10-NEXT: s_andn2_b32 s2, s2, s6
-; GFX10-NEXT: v_writelane_b32 v0, s4, s3
-; GFX10-NEXT: v_add_f32_e32 v1, s5, v1
-; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX10-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX10-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: ; implicit-def: $vgpr2
+; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX10-NEXT: s_mov_b32 s6, exec_lo
+; GFX10-NEXT: ; implicit-def: $vgpr1
+; GFX10-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_add_i32 s3, s3, 4
-; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo
-; GFX10-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX10-NEXT: s_cbranch_execz .LBB28_4
-; GFX10-NEXT: ; %bb.3:
+; GFX10-NEXT: s_add_i32 s3, s5, 4
+; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX10-NEXT: s_cbranch_execz .LBB28_2
+; GFX10-NEXT: ; %bb.1:
+; GFX10-NEXT: s_bcnt1_i32_b32 s5, s6
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s5
; GFX10-NEXT: s_lshl_b32 s5, s3, 3
; GFX10-NEXT: v_mov_b32_e32 v2, s5
-; GFX10-NEXT: ds_add_rtn_f32 v2, v2, v1
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX10-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: .LBB28_4:
+; GFX10-NEXT: .LBB28_2:
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX10-NEXT: s_mov_b32 s6, exec_lo
-; GFX10-NEXT: v_readfirstlane_b32 s4, v2
-; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: s_and_saveexec_b32 s5, vcc_lo
-; GFX10-NEXT: s_cbranch_execz .LBB28_6
-; GFX10-NEXT: ; %bb.5:
-; GFX10-NEXT: s_bcnt1_i32_b32 s6, s6
-; GFX10-NEXT: s_lshl_b32 s3, s3, 4
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX10-NEXT: v_mov_b32_e32 v2, s3
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX10-NEXT: s_mov_b32 s7, exec_lo
+; GFX10-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v2
+; GFX10-NEXT: s_and_saveexec_b32 s6, s2
+; GFX10-NEXT: s_cbranch_execz .LBB28_4
+; GFX10-NEXT: ; %bb.3:
+; GFX10-NEXT: s_bcnt1_i32_b32 s2, s7
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX10-NEXT: s_lshl_b32 s2, s3, 4
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_add_f32 v2, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: .LBB28_6:
+; GFX10-NEXT: .LBB28_4:
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: v_add_f32_e32 v2, s4, v0
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX10-NEXT: s_mov_b32 s3, exec_lo
+; GFX10-NEXT: s_mov_b32 s2, exec_lo
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX10-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, s5, vcc_lo
; GFX10-NEXT: ; implicit-def: $vgpr0
-; GFX10-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX10-NEXT: .LBB28_5: ; %ComputeLoop
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_ff1_i32_b32 s4, s3
+; GFX10-NEXT: s_ff1_i32_b32 s3, s2
; GFX10-NEXT: v_readfirstlane_b32 s5, v1
-; GFX10-NEXT: v_readlane_b32 s6, v2, s4
-; GFX10-NEXT: s_lshl_b32 s7, 1, s4
-; GFX10-NEXT: s_andn2_b32 s3, s3, s7
-; GFX10-NEXT: v_writelane_b32 v0, s5, s4
+; GFX10-NEXT: v_readlane_b32 s6, v2, s3
+; GFX10-NEXT: s_lshl_b32 s7, 1, s3
+; GFX10-NEXT: s_andn2_b32 s2, s2, s7
+; GFX10-NEXT: v_writelane_b32 v0, s5, s3
; GFX10-NEXT: v_add_f32_e32 v1, s6, v1
-; GFX10-NEXT: s_cmp_lg_u32 s3, 0
-; GFX10-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX10-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX10-NEXT: ; %bb.6: ; %ComputeEnd
; GFX10-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo
-; GFX10-NEXT: s_xor_b32 s3, exec_lo, s3
-; GFX10-NEXT: s_cbranch_execz .LBB28_10
-; GFX10-NEXT: ; %bb.9:
-; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX10-NEXT: s_xor_b32 s2, exec_lo, s2
+; GFX10-NEXT: s_cbranch_execz .LBB28_8
+; GFX10-NEXT: ; %bb.7:
+; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: buffer_gl0_inv
-; GFX10-NEXT: .LBB28_10:
+; GFX10-NEXT: .LBB28_8:
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX90A-LABEL: local_ds_fadd:
; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX90A-NEXT: s_mov_b64 s[2:3], exec
-; GFX90A-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX90A-NEXT: ; implicit-def: $vgpr0
-; GFX90A-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX90A-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX90A-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX90A-NEXT: v_readfirstlane_b32 s7, v1
-; GFX90A-NEXT: v_readlane_b32 s8, v2, s6
-; GFX90A-NEXT: s_mov_b32 m0, s6
-; GFX90A-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX90A-NEXT: v_writelane_b32 v0, s7, m0
-; GFX90A-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX90A-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX90A-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX90A-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: s_add_i32 s3, s3, 4
-; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX90A-NEXT: s_add_i32 s5, s5, 4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX90A-NEXT: s_cbranch_execz .LBB28_2
+; GFX90A-NEXT: ; %bb.1:
+; GFX90A-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX90A-NEXT: s_lshl_b32 s8, s5, 3
+; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX90A-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, s8
+; GFX90A-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: .LBB28_2:
+; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX90A-NEXT: s_mov_b64 s[8:9], exec
+; GFX90A-NEXT: v_readfirstlane_b32 s10, v1
+; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX90A-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX90A-NEXT: s_cbranch_execz .LBB28_4
; GFX90A-NEXT: ; %bb.3:
-; GFX90A-NEXT: s_lshl_b32 s6, s3, 3
-; GFX90A-NEXT: v_mov_b32_e32 v2, s6
-; GFX90A-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: .LBB28_4:
-; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX90A-NEXT: s_mov_b64 s[6:7], exec
-; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX90A-NEXT: v_readfirstlane_b32 s8, v2
-; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX90A-NEXT: s_cbranch_execz .LBB28_6
-; GFX90A-NEXT: ; %bb.5:
-; GFX90A-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX90A-NEXT: s_lshl_b32 s3, s3, 4
+; GFX90A-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX90A-NEXT: s_lshl_b32 s2, s5, 4
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX90A-NEXT: v_mov_b32_e32 v2, s3
+; GFX90A-NEXT: v_mov_b32_e32 v2, s2
; GFX90A-NEXT: ds_add_f32 v2, v1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: .LBB28_6:
-; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX90A-NEXT: s_mov_b64 s[4:5], exec
-; GFX90A-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX90A-NEXT: .LBB28_4:
+; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX90A-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX90A-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, s10
+; GFX90A-NEXT: s_mov_b64 s[2:3], exec
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX90A-NEXT: v_bfrev_b32_e32 v1, 1
; GFX90A-NEXT: ; implicit-def: $vgpr0
-; GFX90A-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX90A-NEXT: .LBB28_5: ; %ComputeLoop
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX90A-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX90A-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX90A-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX90A-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX90A-NEXT: v_readfirstlane_b32 s8, v1
-; GFX90A-NEXT: v_readlane_b32 s9, v2, s3
-; GFX90A-NEXT: s_mov_b32 m0, s3
-; GFX90A-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX90A-NEXT: v_readlane_b32 s9, v2, s5
+; GFX90A-NEXT: s_mov_b32 m0, s5
+; GFX90A-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX90A-NEXT: v_writelane_b32 v0, s8, m0
-; GFX90A-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX90A-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX90A-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX90A-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX90A-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX90A-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX90A-NEXT: ; %bb.6: ; %ComputeEnd
; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX90A-NEXT: ; implicit-def: $vgpr2
-; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX90A-NEXT: s_cbranch_execz .LBB28_10
-; GFX90A-NEXT: ; %bb.9:
-; GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GFX90A-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX90A-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX90A-NEXT: s_cbranch_execz .LBB28_8
+; GFX90A-NEXT: ; %bb.7:
+; GFX90A-NEXT: v_mov_b32_e32 v2, s4
; GFX90A-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: .LBB28_10:
-; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX90A-NEXT: .LBB28_8:
+; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX90A-NEXT: v_readfirstlane_b32 s2, v2
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
; GFX90A-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
; GFX90A-NEXT: s_endpgm
;
; GFX908-LABEL: local_ds_fadd:
; GFX908: ; %bb.0:
+; GFX908-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX908-NEXT: s_mov_b64 s[2:3], exec
-; GFX908-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX908-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX908-NEXT: ; implicit-def: $vgpr0
-; GFX908-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX908-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX908-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX908-NEXT: v_readfirstlane_b32 s7, v1
-; GFX908-NEXT: v_readlane_b32 s8, v2, s6
-; GFX908-NEXT: s_mov_b32 m0, s6
-; GFX908-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX908-NEXT: v_writelane_b32 v0, s7, m0
-; GFX908-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX908-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX908-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX908-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX908-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX908-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX908-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX908-NEXT: ; implicit-def: $vgpr2
+; GFX908-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX908-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: s_add_i32 s3, s3, 4
-; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX908-NEXT: s_add_i32 s5, s5, 4
+; GFX908-NEXT: ; implicit-def: $vgpr1
+; GFX908-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX908-NEXT: s_cbranch_execz .LBB28_2
+; GFX908-NEXT: ; %bb.1:
+; GFX908-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX908-NEXT: s_lshl_b32 s8, s5, 3
+; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX908-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX908-NEXT: v_mov_b32_e32 v2, s8
+; GFX908-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX908-NEXT: s_waitcnt lgkmcnt(0)
+; GFX908-NEXT: .LBB28_2:
+; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX908-NEXT: s_mov_b64 s[8:9], exec
+; GFX908-NEXT: v_readfirstlane_b32 s10, v1
+; GFX908-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX908-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX908-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX908-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_cbranch_execz .LBB28_4
; GFX908-NEXT: ; %bb.3:
-; GFX908-NEXT: s_lshl_b32 s6, s3, 3
-; GFX908-NEXT: v_mov_b32_e32 v2, s6
-; GFX908-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: .LBB28_4:
-; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: s_mov_b64 s[6:7], exec
-; GFX908-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX908-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX908-NEXT: v_readfirstlane_b32 s8, v2
-; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX908-NEXT: s_cbranch_execz .LBB28_6
-; GFX908-NEXT: ; %bb.5:
-; GFX908-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX908-NEXT: s_lshl_b32 s3, s3, 4
+; GFX908-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX908-NEXT: s_lshl_b32 s2, s5, 4
; GFX908-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX908-NEXT: v_mov_b32_e32 v2, s3
+; GFX908-NEXT: v_mov_b32_e32 v2, s2
; GFX908-NEXT: ds_add_f32 v2, v1
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: .LBB28_6:
-; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: s_mov_b64 s[4:5], exec
-; GFX908-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX908-NEXT: .LBB28_4:
+; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX908-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX908-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX908-NEXT: v_mov_b32_e32 v1, s10
+; GFX908-NEXT: s_mov_b64 s[2:3], exec
+; GFX908-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX908-NEXT: v_bfrev_b32_e32 v1, 1
; GFX908-NEXT: ; implicit-def: $vgpr0
-; GFX908-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX908-NEXT: .LBB28_5: ; %ComputeLoop
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX908-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX908-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX908-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX908-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX908-NEXT: v_readfirstlane_b32 s8, v1
-; GFX908-NEXT: v_readlane_b32 s9, v2, s3
-; GFX908-NEXT: s_mov_b32 m0, s3
-; GFX908-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX908-NEXT: v_readlane_b32 s9, v2, s5
+; GFX908-NEXT: s_mov_b32 m0, s5
+; GFX908-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX908-NEXT: v_writelane_b32 v0, s8, m0
-; GFX908-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX908-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX908-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX908-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX908-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX908-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX908-NEXT: ; %bb.6: ; %ComputeEnd
; GFX908-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX908-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX908-NEXT: ; implicit-def: $vgpr2
-; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB28_10
-; GFX908-NEXT: ; %bb.9:
-; GFX908-NEXT: v_mov_b32_e32 v2, s2
+; GFX908-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX908-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX908-NEXT: s_cbranch_execz .LBB28_8
+; GFX908-NEXT: ; %bb.7:
+; GFX908-NEXT: v_mov_b32_e32 v2, s4
; GFX908-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: .LBB28_10:
-; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: .LBB28_8:
+; GFX908-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX908-NEXT: v_readfirstlane_b32 s2, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, 0
; GFX908-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX908-NEXT: v_mov_b32_e32 v2, s2
+; GFX908-NEXT: v_mov_b32_e32 v1, 0
+; GFX908-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: global_store_dword v1, v0, s[0:1]
; GFX908-NEXT: s_endpgm
;
; GFX8-LABEL: local_ds_fadd:
; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX8-NEXT: s_mov_b64 s[2:3], exec
-; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX8-NEXT: ; implicit-def: $vgpr0
-; GFX8-NEXT: .LBB28_1: ; %ComputeLoop
-; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX8-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX8-NEXT: v_readfirstlane_b32 s7, v1
-; GFX8-NEXT: v_readlane_b32 s8, v2, s6
-; GFX8-NEXT: s_mov_b32 m0, s6
-; GFX8-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX8-NEXT: v_writelane_b32 v0, s7, m0
-; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX8-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX8-NEXT: s_cbranch_scc1 .LBB28_1
-; GFX8-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX8-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
-; GFX8-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; GFX8-NEXT: ; implicit-def: $vgpr2
+; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_add_i32 s5, s5, 4
+; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_mov_b32 m0, -1
+; GFX8-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX8-NEXT: s_cbranch_execz .LBB28_2
+; GFX8-NEXT: ; %bb.1:
+; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX8-NEXT: s_lshl_b32 s8, s5, 3
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NEXT: ds_add_rtn_f32 v1, v2, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_add_i32 s3, s3, 4
-; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX8-NEXT: .LBB28_2:
+; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX8-NEXT: s_mov_b64 s[8:9], exec
+; GFX8-NEXT: v_readfirstlane_b32 s10, v1
+; GFX8-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX8-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX8-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX8-NEXT: s_cbranch_execz .LBB28_4
; GFX8-NEXT: ; %bb.3:
-; GFX8-NEXT: s_lshl_b32 s6, s3, 3
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: .LBB28_4:
-; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: s_mov_b64 s[6:7], exec
-; GFX8-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX8-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX8-NEXT: v_readfirstlane_b32 s8, v2
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX8-NEXT: s_cbranch_execz .LBB28_6
-; GFX8-NEXT: ; %bb.5:
-; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX8-NEXT: s_lshl_b32 s3, s3, 4
+; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX8-NEXT: s_lshl_b32 s2, s5, 4
; GFX8-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: ds_add_f32 v2, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: .LBB28_6:
-; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: s_mov_b64 s[4:5], exec
-; GFX8-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX8-NEXT: .LBB28_4:
+; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX8-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, s10
+; GFX8-NEXT: s_mov_b64 s[2:3], exec
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: ; implicit-def: $vgpr0
-; GFX8-NEXT: .LBB28_7: ; %ComputeLoop1
+; GFX8-NEXT: .LBB28_5: ; %ComputeLoop
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX8-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX8-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX8-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX8-NEXT: v_readfirstlane_b32 s8, v1
-; GFX8-NEXT: v_readlane_b32 s9, v2, s3
-; GFX8-NEXT: s_mov_b32 m0, s3
-; GFX8-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX8-NEXT: v_readlane_b32 s9, v2, s5
+; GFX8-NEXT: s_mov_b32 m0, s5
+; GFX8-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX8-NEXT: v_writelane_b32 v0, s8, m0
-; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX8-NEXT: s_cbranch_scc1 .LBB28_7
-; GFX8-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX8-NEXT: s_cbranch_scc1 .LBB28_5
+; GFX8-NEXT: ; %bb.6: ; %ComputeEnd
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr2
-; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX8-NEXT: s_cbranch_execz .LBB28_10
-; GFX8-NEXT: ; %bb.9:
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX8-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX8-NEXT: s_cbranch_execz .LBB28_8
+; GFX8-NEXT: ; %bb.7:
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_add_rtn_f32 v2, v2, v1
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: .LBB28_10:
-; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX8-NEXT: .LBB28_8:
+; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX8-NEXT: v_readfirstlane_b32 s2, v2
-; GFX8-NEXT: v_add_f32_e32 v2, s2, v0
+; GFX8-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
@@ -7639,153 +7582,186 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
;
; GFX7-LABEL: local_ds_fadd:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2
-; GFX7-NEXT: s_mov_b32 m0, -1
+; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2
+; GFX7-NEXT: s_mov_b64 s[2:3], exec
+; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
+; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_lshl_b32 s4, s3, 3
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-NEXT: ds_read_b32 v0, v0 offset:32
-; GFX7-NEXT: s_add_i32 s3, s3, 4
-; GFX7-NEXT: s_lshl_b32 s6, s3, 3
-; GFX7-NEXT: s_mov_b64 s[4:5], 0
-; GFX7-NEXT: v_mov_b32_e32 v1, s6
-; GFX7-NEXT: .LBB28_1: ; %atomicrmw.start
+; GFX7-NEXT: s_add_i32 s5, s5, 4
+; GFX7-NEXT: ; implicit-def: $vgpr1
+; GFX7-NEXT: s_mov_b32 m0, -1
+; GFX7-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX7-NEXT: s_cbranch_execz .LBB28_4
+; GFX7-NEXT: ; %bb.1:
+; GFX7-NEXT: s_lshl_b32 s8, s5, 3
+; GFX7-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-NEXT: ds_read_b32 v1, v2
+; GFX7-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v3, s2
+; GFX7-NEXT: v_mul_f32_e32 v3, 0x42280000, v3
+; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: .LBB28_2: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v2, v0
-; GFX7-NEXT: v_add_f32_e32 v0, 0x42280000, v2
-; GFX7-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
+; GFX7-NEXT: v_mov_b32_e32 v4, v1
+; GFX7-NEXT: v_add_f32_e32 v1, v4, v3
+; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v2, v4, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
-; GFX7-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GFX7-NEXT: s_cbranch_execnz .LBB28_1
-; GFX7-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX7-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX7-NEXT: s_mov_b64 s[6:7], exec
-; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s6, 0
-; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s7, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX7-NEXT: s_cbranch_execz .LBB28_5
-; GFX7-NEXT: ; %bb.3:
-; GFX7-NEXT: s_lshl_b32 s3, s3, 4
-; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], v1, v4
+; GFX7-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
+; GFX7-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX7-NEXT: s_cbranch_execnz .LBB28_2
+; GFX7-NEXT: ; %bb.3: ; %Flow18
+; GFX7-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX7-NEXT: .LBB28_4: ; %Flow19
+; GFX7-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX7-NEXT: s_mov_b64 s[8:9], exec
+; GFX7-NEXT: v_readfirstlane_b32 s10, v1
+; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s8, 0
+; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s9, v1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX7-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
+; GFX7-NEXT: s_cbranch_execz .LBB28_7
+; GFX7-NEXT: ; %bb.5:
+; GFX7-NEXT: s_lshl_b32 s2, s5, 4
+; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: ds_read_b32 v3, v1
-; GFX7-NEXT: s_bcnt1_i32_b64 s3, s[6:7]
-; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v2, s3
+; GFX7-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
; GFX7-NEXT: v_mul_f32_e32 v2, 0x42280000, v2
-; GFX7-NEXT: s_mov_b64 s[6:7], 0
-; GFX7-NEXT: .LBB28_4: ; %atomicrmw.start2
+; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: .LBB28_6: ; %atomicrmw.start2
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_add_f32_e32 v4, v3, v2
; GFX7-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
-; GFX7-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], v4, v3
+; GFX7-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
; GFX7-NEXT: v_mov_b32_e32 v3, v4
-; GFX7-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX7-NEXT: s_cbranch_execnz .LBB28_4
-; GFX7-NEXT: .LBB28_5: ; %Flow17
-; GFX7-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-NEXT: ds_read_b32 v1, v2
+; GFX7-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX7-NEXT: s_cbranch_execnz .LBB28_6
+; GFX7-NEXT: .LBB28_7: ; %Flow17
+; GFX7-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_mul_f32_e32 v2, 0x42280000, v0
+; GFX7-NEXT: ds_read_b32 v0, v1
+; GFX7-NEXT: v_add_f32_e32 v2, s10, v2
+; GFX7-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX7-NEXT: s_mov_b64 s[2:3], 0
-; GFX7-NEXT: .LBB28_6: ; %atomicrmw.start8
+; GFX7-NEXT: .LBB28_8: ; %atomicrmw.start8
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, v1
-; GFX7-NEXT: v_add_f32_e32 v1, v3, v0
-; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v2, v3, v1
+; GFX7-NEXT: v_mov_b32_e32 v3, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v3, v2
+; GFX7-NEXT: ds_cmpst_rtn_b32 v0, v1, v3, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v0, v3
; GFX7-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX7-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX7-NEXT: s_cbranch_execnz .LBB28_6
-; GFX7-NEXT: ; %bb.7: ; %atomicrmw.end7
+; GFX7-NEXT: s_cbranch_execnz .LBB28_8
+; GFX7-NEXT: ; %bb.9: ; %atomicrmw.end7
; GFX7-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX6-LABEL: local_ds_fadd:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2
-; GFX6-NEXT: s_mov_b32 m0, -1
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2
+; GFX6-NEXT: s_mov_b64 s[2:3], exec
+; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
+; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b32 s4, s3, 3
-; GFX6-NEXT: s_add_i32 s4, s4, 32
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
-; GFX6-NEXT: ds_read_b32 v0, v0
-; GFX6-NEXT: s_add_i32 s3, s3, 4
-; GFX6-NEXT: s_lshl_b32 s6, s3, 3
-; GFX6-NEXT: s_mov_b64 s[4:5], 0
-; GFX6-NEXT: v_mov_b32_e32 v1, s6
-; GFX6-NEXT: .LBB28_1: ; %atomicrmw.start
+; GFX6-NEXT: s_add_i32 s5, s5, 4
+; GFX6-NEXT: ; implicit-def: $vgpr1
+; GFX6-NEXT: s_mov_b32 m0, -1
+; GFX6-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX6-NEXT: s_cbranch_execz .LBB28_4
+; GFX6-NEXT: ; %bb.1:
+; GFX6-NEXT: s_lshl_b32 s8, s5, 3
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: ds_read_b32 v1, v2
+; GFX6-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, s2
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x42280000, v3
+; GFX6-NEXT: s_mov_b64 s[8:9], 0
+; GFX6-NEXT: .LBB28_2: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v0
-; GFX6-NEXT: v_add_f32_e32 v0, 0x42280000, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
+; GFX6-NEXT: v_mov_b32_e32 v4, v1
+; GFX6-NEXT: v_add_f32_e32 v1, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v2, v4, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
-; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GFX6-NEXT: s_cbranch_execnz .LBB28_1
-; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: s_mov_b64 s[6:7], exec
-; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s6, 0
-; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s7, v1
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX6-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX6-NEXT: s_cbranch_execz .LBB28_5
-; GFX6-NEXT: ; %bb.3:
-; GFX6-NEXT: s_lshl_b32 s3, s3, 4
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], v1, v4
+; GFX6-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
+; GFX6-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX6-NEXT: s_cbranch_execnz .LBB28_2
+; GFX6-NEXT: ; %bb.3: ; %Flow16
+; GFX6-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX6-NEXT: .LBB28_4: ; %Flow17
+; GFX6-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX6-NEXT: s_mov_b64 s[8:9], exec
+; GFX6-NEXT: v_readfirstlane_b32 s10, v1
+; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s8, 0
+; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s9, v1
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX6-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
+; GFX6-NEXT: s_cbranch_execz .LBB28_7
+; GFX6-NEXT: ; %bb.5:
+; GFX6-NEXT: s_lshl_b32 s2, s5, 4
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: ds_read_b32 v3, v1
-; GFX6-NEXT: s_bcnt1_i32_b64 s3, s[6:7]
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s3
+; GFX6-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
; GFX6-NEXT: v_mul_f32_e32 v2, 0x42280000, v2
-; GFX6-NEXT: s_mov_b64 s[6:7], 0
-; GFX6-NEXT: .LBB28_4: ; %atomicrmw.start2
+; GFX6-NEXT: s_mov_b64 s[8:9], 0
+; GFX6-NEXT: .LBB28_6: ; %atomicrmw.start2
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_add_f32_e32 v4, v3, v2
; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
-; GFX6-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], v4, v3
+; GFX6-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
; GFX6-NEXT: v_mov_b32_e32 v3, v4
-; GFX6-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX6-NEXT: s_cbranch_execnz .LBB28_4
-; GFX6-NEXT: .LBB28_5: ; %Flow15
-; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v2, s2
-; GFX6-NEXT: ds_read_b32 v1, v2
+; GFX6-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX6-NEXT: s_cbranch_execnz .LBB28_6
+; GFX6-NEXT: .LBB28_7: ; %Flow15
+; GFX6-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, s4
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x42280000, v0
+; GFX6-NEXT: ds_read_b32 v0, v1
+; GFX6-NEXT: v_add_f32_e32 v2, s10, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, s10
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: s_mov_b64 s[2:3], 0
-; GFX6-NEXT: .LBB28_6: ; %atomicrmw.start8
+; GFX6-NEXT: .LBB28_8: ; %atomicrmw.start8
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v3, v1
-; GFX6-NEXT: v_add_f32_e32 v1, v3, v0
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v2, v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, v0
+; GFX6-NEXT: v_add_f32_e32 v0, v3, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v3, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v3
; GFX6-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX6-NEXT: s_cbranch_execnz .LBB28_6
-; GFX6-NEXT: ; %bb.7: ; %atomicrmw.end7
+; GFX6-NEXT: s_cbranch_execnz .LBB28_8
+; GFX6-NEXT: ; %bb.9: ; %atomicrmw.end7
; GFX6-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
%idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 3
@@ -7802,91 +7778,84 @@ define amdgpu_kernel void @local_ds_fadd(ptr addrspace(1) %out, ptr addrspace(3)
define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrspace(3) %ptrf, i32 %idx) {
; GFX12-LABEL: local_ds_fadd_one_as:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_mov_b32_e32 v1, 0x42280000
-; GFX12-NEXT: s_mov_b32 s2, exec_lo
-; GFX12-NEXT: s_brev_b32 s4, 1
-; GFX12-NEXT: ; implicit-def: $vgpr0
-; GFX12-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_ctz_i32_b32 s3, s2
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: v_readlane_b32 s5, v1, s3
-; GFX12-NEXT: s_lshl_b32 s6, 1, s3
-; GFX12-NEXT: v_writelane_b32 v0, s4, s3
-; GFX12-NEXT: s_and_not1_b32 s2, s2, s6
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_lg_u32 s2, 0
-; GFX12-NEXT: s_add_f32 s4, s4, s5
-; GFX12-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX12-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX12-NEXT: s_load_b64 s[2:3], s[0:1], 0x8
-; GFX12-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
+; GFX12-NEXT: s_load_b64 s[4:5], s[0:1], 0x8
+; GFX12-NEXT: s_mov_b32 s6, exec_lo
; GFX12-NEXT: ; implicit-def: $vgpr1
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: s_add_co_i32 s3, s3, 4
-; GFX12-NEXT: s_and_saveexec_b32 s5, vcc_lo
-; GFX12-NEXT: s_xor_b32 s5, exec_lo, s5
-; GFX12-NEXT: s_cbranch_execz .LBB29_4
-; GFX12-NEXT: ; %bb.3:
-; GFX12-NEXT: s_lshl_b32 s6, s3, 3
+; GFX12-NEXT: s_add_co_i32 s3, s5, 4
+; GFX12-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX12-NEXT: s_cbranch_execz .LBB29_2
+; GFX12-NEXT: ; %bb.1:
+; GFX12-NEXT: s_bcnt1_i32_b32 s5, s6
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s6
-; GFX12-NEXT: ds_add_rtn_f32 v1, v1, v2
-; GFX12-NEXT: .LBB29_4:
-; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s5
+; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s5
+; GFX12-NEXT: s_lshl_b32 s5, s3, 3
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX12-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX12-NEXT: .LBB29_2:
+; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX12-NEXT: s_mov_b32 s6, exec_lo
+; GFX12-NEXT: s_mov_b32 s7, exec_lo
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
-; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, s6, 0
-; GFX12-NEXT: s_mov_b32 s4, exec_lo
+; GFX12-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
+; GFX12-NEXT: s_mov_b32 s6, exec_lo
; GFX12-NEXT: v_cmpx_eq_u32_e32 0, v2
-; GFX12-NEXT: s_cbranch_execz .LBB29_6
-; GFX12-NEXT: ; %bb.5:
-; GFX12-NEXT: s_bcnt1_i32_b32 s6, s6
-; GFX12-NEXT: s_lshl_b32 s3, s3, 4
-; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX12-NEXT: s_cbranch_execz .LBB29_4
+; GFX12-NEXT: ; %bb.3:
+; GFX12-NEXT: s_bcnt1_i32_b32 s2, s7
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX12-NEXT: s_lshl_b32 s2, s3, 4
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX12-NEXT: ds_add_f32 v2, v1
-; GFX12-NEXT: .LBB29_6:
-; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX12-NEXT: v_add_f32_e32 v1, s5, v0
-; GFX12-NEXT: s_mov_b32 s4, exec_lo
-; GFX12-NEXT: s_brev_b32 s3, 1
+; GFX12-NEXT: .LBB29_4:
+; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX12-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX12-NEXT: s_mov_b32 s3, exec_lo
+; GFX12-NEXT: s_brev_b32 s2, 1
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX12-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: v_cndmask_b32_e64 v1, v0, s5, vcc_lo
; GFX12-NEXT: ; implicit-def: $vgpr0
-; GFX12-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX12-NEXT: .LBB29_5: ; %ComputeLoop
; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX12-NEXT: s_ctz_i32_b32 s5, s4
+; GFX12-NEXT: s_ctz_i32_b32 s5, s3
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: v_readlane_b32 s6, v1, s5
; GFX12-NEXT: s_lshl_b32 s7, 1, s5
-; GFX12-NEXT: v_writelane_b32 v0, s3, s5
-; GFX12-NEXT: s_and_not1_b32 s4, s4, s7
+; GFX12-NEXT: v_writelane_b32 v0, s2, s5
+; GFX12-NEXT: s_and_not1_b32 s3, s3, s7
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: s_cmp_lg_u32 s4, 0
-; GFX12-NEXT: s_add_f32 s3, s3, s6
-; GFX12-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX12-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX12-NEXT: s_cmp_lg_u32 s3, 0
+; GFX12-NEXT: s_add_f32 s2, s2, s6
+; GFX12-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX12-NEXT: ; %bb.6: ; %ComputeEnd
; GFX12-NEXT: v_mbcnt_lo_u32_b32 v1, exec_lo, 0
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
; GFX12-NEXT: ; implicit-def: $vgpr1
-; GFX12-NEXT: s_and_saveexec_b32 s4, vcc_lo
-; GFX12-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX12-NEXT: s_cbranch_execz .LBB29_10
-; GFX12-NEXT: ; %bb.9:
-; GFX12-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3
+; GFX12-NEXT: s_and_saveexec_b32 s3, vcc_lo
+; GFX12-NEXT: s_xor_b32 s3, exec_lo, s3
+; GFX12-NEXT: s_cbranch_execz .LBB29_8
+; GFX12-NEXT: ; %bb.7:
+; GFX12-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s2
; GFX12-NEXT: ds_add_rtn_f32 v1, v1, v2
-; GFX12-NEXT: .LBB29_10:
-; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX12-NEXT: .LBB29_8:
+; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s3
; GFX12-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX12-NEXT: s_wait_dscnt 0x0
; GFX12-NEXT: v_readfirstlane_b32 s2, v1
-; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s2, v0
+; GFX12-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX12-NEXT: s_nop 0
@@ -7895,185 +7864,168 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
;
; GFX940-LABEL: local_ds_fadd_one_as:
; GFX940: ; %bb.0:
+; GFX940-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX940-NEXT: s_mov_b64 s[2:3], exec
-; GFX940-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX940-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX940-NEXT: ; implicit-def: $vgpr0
-; GFX940-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX940-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX940-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX940-NEXT: v_readfirstlane_b32 s7, v1
-; GFX940-NEXT: v_readlane_b32 s8, v2, s6
-; GFX940-NEXT: s_mov_b32 m0, s6
-; GFX940-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX940-NEXT: v_writelane_b32 v0, s7, m0
-; GFX940-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX940-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX940-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX940-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX940-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX940-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX940-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX940-NEXT: ; implicit-def: $vgpr2
+; GFX940-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX940-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-NEXT: s_add_i32 s3, s3, 4
-; GFX940-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX940-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX940-NEXT: s_add_i32 s5, s5, 4
+; GFX940-NEXT: ; implicit-def: $vgpr1
+; GFX940-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX940-NEXT: s_cbranch_execz .LBB29_2
+; GFX940-NEXT: ; %bb.1:
+; GFX940-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX940-NEXT: s_lshl_b32 s8, s5, 3
+; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX940-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX940-NEXT: v_mov_b32_e32 v2, s8
+; GFX940-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX940-NEXT: .LBB29_2:
+; GFX940-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX940-NEXT: s_mov_b64 s[8:9], exec
+; GFX940-NEXT: s_waitcnt lgkmcnt(0)
+; GFX940-NEXT: v_readfirstlane_b32 s10, v1
+; GFX940-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX940-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX940-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX940-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX940-NEXT: s_cbranch_execz .LBB29_4
; GFX940-NEXT: ; %bb.3:
-; GFX940-NEXT: s_lshl_b32 s6, s3, 3
-; GFX940-NEXT: v_mov_b32_e32 v2, s6
-; GFX940-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX940-NEXT: .LBB29_4:
-; GFX940-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX940-NEXT: s_mov_b64 s[6:7], exec
-; GFX940-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX940-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX940-NEXT: s_waitcnt lgkmcnt(0)
-; GFX940-NEXT: v_readfirstlane_b32 s8, v2
-; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX940-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX940-NEXT: s_cbranch_execz .LBB29_6
-; GFX940-NEXT: ; %bb.5:
-; GFX940-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX940-NEXT: s_lshl_b32 s3, s3, 4
+; GFX940-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX940-NEXT: s_lshl_b32 s2, s5, 4
; GFX940-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX940-NEXT: v_mov_b32_e32 v2, s3
+; GFX940-NEXT: v_mov_b32_e32 v2, s2
; GFX940-NEXT: ds_add_f32 v2, v1
-; GFX940-NEXT: .LBB29_6:
-; GFX940-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX940-NEXT: s_mov_b64 s[4:5], exec
-; GFX940-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX940-NEXT: .LBB29_4:
+; GFX940-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX940-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX940-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX940-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX940-NEXT: v_mov_b32_e32 v1, s10
+; GFX940-NEXT: s_mov_b64 s[2:3], exec
+; GFX940-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX940-NEXT: v_bfrev_b32_e32 v1, 1
; GFX940-NEXT: ; implicit-def: $vgpr0
-; GFX940-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX940-NEXT: .LBB29_5: ; %ComputeLoop
; GFX940-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX940-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX940-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX940-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX940-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX940-NEXT: v_readfirstlane_b32 s8, v1
-; GFX940-NEXT: v_readlane_b32 s9, v2, s3
-; GFX940-NEXT: s_mov_b32 m0, s3
-; GFX940-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX940-NEXT: v_readlane_b32 s9, v2, s5
+; GFX940-NEXT: s_mov_b32 m0, s5
+; GFX940-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX940-NEXT: v_writelane_b32 v0, s8, m0
-; GFX940-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX940-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX940-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX940-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX940-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX940-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX940-NEXT: ; %bb.6: ; %ComputeEnd
; GFX940-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX940-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX940-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX940-NEXT: ; implicit-def: $vgpr2
-; GFX940-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX940-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX940-NEXT: s_cbranch_execz .LBB29_10
-; GFX940-NEXT: ; %bb.9:
-; GFX940-NEXT: v_mov_b32_e32 v2, s2
+; GFX940-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX940-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX940-NEXT: s_cbranch_execz .LBB29_8
+; GFX940-NEXT: ; %bb.7:
+; GFX940-NEXT: v_mov_b32_e32 v2, s4
; GFX940-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX940-NEXT: .LBB29_10:
-; GFX940-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX940-NEXT: .LBB29_8:
+; GFX940-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX940-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX940-NEXT: s_waitcnt lgkmcnt(0)
; GFX940-NEXT: v_readfirstlane_b32 s2, v2
; GFX940-NEXT: v_mov_b32_e32 v1, 0
; GFX940-NEXT: s_nop 0
; GFX940-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX940-NEXT: v_mov_b32_e32 v2, s2
+; GFX940-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX940-NEXT: global_store_dword v1, v0, s[0:1] sc0 sc1
; GFX940-NEXT: s_endpgm
;
; GFX11-LABEL: local_ds_fadd_one_as:
; GFX11: ; %bb.0:
-; GFX11-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX11-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX11-NEXT: s_mov_b32 s2, exec_lo
-; GFX11-NEXT: ; implicit-def: $vgpr0
-; GFX11-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
+; GFX11-NEXT: s_load_b64 s[4:5], s[0:1], 0x8
+; GFX11-NEXT: s_mov_b32 s6, exec_lo
+; GFX11-NEXT: ; implicit-def: $vgpr1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_ctz_i32_b32 s3, s2
-; GFX11-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_readlane_b32 s5, v2, s3
-; GFX11-NEXT: s_lshl_b32 s6, 1, s3
-; GFX11-NEXT: s_and_not1_b32 s2, s2, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: v_writelane_b32 v0, s4, s3
-; GFX11-NEXT: v_add_f32_e32 v1, s5, v1
-; GFX11-NEXT: s_cmp_lg_u32 s2, 0
-; GFX11-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX11-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX11-NEXT: s_load_b64 s[2:3], s[0:1], 0x8
-; GFX11-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_1)
-; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX11-NEXT: ; implicit-def: $vgpr2
+; GFX11-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: s_add_i32 s3, s3, 4
-; GFX11-NEXT: s_and_saveexec_b32 s4, vcc_lo
-; GFX11-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX11-NEXT: s_cbranch_execz .LBB29_4
-; GFX11-NEXT: ; %bb.3:
-; GFX11-NEXT: s_lshl_b32 s5, s3, 3
+; GFX11-NEXT: s_add_i32 s3, s5, 4
+; GFX11-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX11-NEXT: s_cbranch_execz .LBB29_2
+; GFX11-NEXT: ; %bb.1:
+; GFX11-NEXT: s_bcnt1_i32_b32 s5, s6
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b32_e32 v2, s5
-; GFX11-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX11-NEXT: .LBB29_4:
-; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s4
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s5
+; GFX11-NEXT: s_lshl_b32 s5, s3, 3
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s5 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX11-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX11-NEXT: .LBB29_2:
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_mov_b32 s6, exec_lo
+; GFX11-NEXT: s_mov_b32 s7, exec_lo
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_readfirstlane_b32 s4, v2
-; GFX11-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX11-NEXT: s_mov_b32 s5, exec_lo
-; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v1
-; GFX11-NEXT: s_cbranch_execz .LBB29_6
-; GFX11-NEXT: ; %bb.5:
-; GFX11-NEXT: s_bcnt1_i32_b32 s6, s6
-; GFX11-NEXT: s_lshl_b32 s3, s3, 4
-; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-NEXT: v_dual_mov_b32 v2, s3 :: v_dual_mul_f32 v1, 0x42280000, v1
+; GFX11-NEXT: v_readfirstlane_b32 s5, v1
+; GFX11-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
+; GFX11-NEXT: s_mov_b32 s6, exec_lo
+; GFX11-NEXT: v_cmpx_eq_u32_e32 0, v2
+; GFX11-NEXT: s_cbranch_execz .LBB29_4
+; GFX11-NEXT: ; %bb.3:
+; GFX11-NEXT: s_bcnt1_i32_b32 s2, s7
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX11-NEXT: s_lshl_b32 s2, s3, 4
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mul_f32 v1, 0x42280000, v1
; GFX11-NEXT: ds_add_f32 v2, v1
-; GFX11-NEXT: .LBB29_6:
-; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX11-NEXT: v_add_f32_e32 v2, s4, v0
+; GFX11-NEXT: .LBB29_4:
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX11-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX11-NEXT: s_mov_b32 s3, exec_lo
+; GFX11-NEXT: s_mov_b32 s2, exec_lo
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX11-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: v_cndmask_b32_e64 v2, v0, s5, vcc_lo
; GFX11-NEXT: ; implicit-def: $vgpr0
-; GFX11-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX11-NEXT: .LBB29_5: ; %ComputeLoop
; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-NEXT: s_ctz_i32_b32 s4, s3
+; GFX11-NEXT: s_ctz_i32_b32 s3, s2
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-NEXT: v_readfirstlane_b32 s5, v1
-; GFX11-NEXT: v_readlane_b32 s6, v2, s4
-; GFX11-NEXT: s_lshl_b32 s7, 1, s4
+; GFX11-NEXT: v_readlane_b32 s6, v2, s3
+; GFX11-NEXT: s_lshl_b32 s7, 1, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-NEXT: s_and_not1_b32 s3, s3, s7
-; GFX11-NEXT: v_writelane_b32 v0, s5, s4
+; GFX11-NEXT: s_and_not1_b32 s2, s2, s7
+; GFX11-NEXT: v_writelane_b32 v0, s5, s3
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT: v_add_f32_e32 v1, s6, v1
-; GFX11-NEXT: s_cmp_lg_u32 s3, 0
-; GFX11-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX11-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX11-NEXT: s_cmp_lg_u32 s2, 0
+; GFX11-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX11-NEXT: ; %bb.6: ; %ComputeEnd
; GFX11-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX11-NEXT: ; implicit-def: $vgpr2
-; GFX11-NEXT: s_and_saveexec_b32 s3, vcc_lo
-; GFX11-NEXT: s_xor_b32 s3, exec_lo, s3
-; GFX11-NEXT: s_cbranch_execz .LBB29_10
-; GFX11-NEXT: ; %bb.9:
-; GFX11-NEXT: v_mov_b32_e32 v2, s2
+; GFX11-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX11-NEXT: s_xor_b32 s2, exec_lo, s2
+; GFX11-NEXT: s_cbranch_execz .LBB29_8
+; GFX11-NEXT: ; %bb.7:
+; GFX11-NEXT: v_mov_b32_e32 v2, s4
; GFX11-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX11-NEXT: .LBB29_10:
-; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX11-NEXT: .LBB29_8:
+; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_readfirstlane_b32 s2, v2
-; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_f32 v0, s2, v0
+; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-NEXT: s_nop 0
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
@@ -8081,357 +8033,324 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
;
; GFX10-LABEL: local_ds_fadd_one_as:
; GFX10: ; %bb.0:
-; GFX10-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX10-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX10-NEXT: s_mov_b32 s2, exec_lo
-; GFX10-NEXT: ; implicit-def: $vgpr0
-; GFX10-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_ff1_i32_b32 s3, s2
-; GFX10-NEXT: v_readfirstlane_b32 s4, v1
-; GFX10-NEXT: v_readlane_b32 s5, v2, s3
-; GFX10-NEXT: s_lshl_b32 s6, 1, s3
-; GFX10-NEXT: s_andn2_b32 s2, s2, s6
-; GFX10-NEXT: v_writelane_b32 v0, s4, s3
-; GFX10-NEXT: v_add_f32_e32 v1, s5, v1
-; GFX10-NEXT: s_cmp_lg_u32 s2, 0
-; GFX10-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX10-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX10-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
-; GFX10-NEXT: ; implicit-def: $vgpr2
+; GFX10-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
+; GFX10-NEXT: s_mov_b32 s6, exec_lo
+; GFX10-NEXT: ; implicit-def: $vgpr1
+; GFX10-NEXT: v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: s_add_i32 s3, s3, 4
-; GFX10-NEXT: s_and_saveexec_b32 s4, vcc_lo
-; GFX10-NEXT: s_xor_b32 s4, exec_lo, s4
-; GFX10-NEXT: s_cbranch_execz .LBB29_4
-; GFX10-NEXT: ; %bb.3:
+; GFX10-NEXT: s_add_i32 s3, s5, 4
+; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX10-NEXT: s_cbranch_execz .LBB29_2
+; GFX10-NEXT: ; %bb.1:
+; GFX10-NEXT: s_bcnt1_i32_b32 s5, s6
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s5
; GFX10-NEXT: s_lshl_b32 s5, s3, 3
; GFX10-NEXT: v_mov_b32_e32 v2, s5
-; GFX10-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX10-NEXT: .LBB29_4:
+; GFX10-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX10-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX10-NEXT: .LBB29_2:
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s4
-; GFX10-NEXT: s_mov_b32 s6, exec_lo
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
+; GFX10-NEXT: s_mov_b32 s7, exec_lo
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
-; GFX10-NEXT: v_readfirstlane_b32 s4, v2
-; GFX10-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1
-; GFX10-NEXT: s_and_saveexec_b32 s5, vcc_lo
-; GFX10-NEXT: s_cbranch_execz .LBB29_6
-; GFX10-NEXT: ; %bb.5:
-; GFX10-NEXT: s_bcnt1_i32_b32 s6, s6
-; GFX10-NEXT: s_lshl_b32 s3, s3, 4
-; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX10-NEXT: v_mov_b32_e32 v2, s3
+; GFX10-NEXT: v_readfirstlane_b32 s5, v1
+; GFX10-NEXT: v_mbcnt_lo_u32_b32 v2, s7, 0
+; GFX10-NEXT: v_cmp_eq_u32_e64 s2, 0, v2
+; GFX10-NEXT: s_and_saveexec_b32 s6, s2
+; GFX10-NEXT: s_cbranch_execz .LBB29_4
+; GFX10-NEXT: ; %bb.3:
+; GFX10-NEXT: s_bcnt1_i32_b32 s2, s7
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX10-NEXT: s_lshl_b32 s2, s3, 4
+; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
; GFX10-NEXT: ds_add_f32 v2, v1
-; GFX10-NEXT: .LBB29_6:
+; GFX10-NEXT: .LBB29_4:
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s5
-; GFX10-NEXT: v_add_f32_e32 v2, s4, v0
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s6
+; GFX10-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
; GFX10-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX10-NEXT: s_mov_b32 s3, exec_lo
+; GFX10-NEXT: s_mov_b32 s2, exec_lo
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX10-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v2, v0, s5, vcc_lo
; GFX10-NEXT: ; implicit-def: $vgpr0
-; GFX10-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX10-NEXT: .LBB29_5: ; %ComputeLoop
; GFX10-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX10-NEXT: s_ff1_i32_b32 s4, s3
+; GFX10-NEXT: s_ff1_i32_b32 s3, s2
; GFX10-NEXT: v_readfirstlane_b32 s5, v1
-; GFX10-NEXT: v_readlane_b32 s6, v2, s4
-; GFX10-NEXT: s_lshl_b32 s7, 1, s4
-; GFX10-NEXT: s_andn2_b32 s3, s3, s7
-; GFX10-NEXT: v_writelane_b32 v0, s5, s4
+; GFX10-NEXT: v_readlane_b32 s6, v2, s3
+; GFX10-NEXT: s_lshl_b32 s7, 1, s3
+; GFX10-NEXT: s_andn2_b32 s2, s2, s7
+; GFX10-NEXT: v_writelane_b32 v0, s5, s3
; GFX10-NEXT: v_add_f32_e32 v1, s6, v1
-; GFX10-NEXT: s_cmp_lg_u32 s3, 0
-; GFX10-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX10-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX10-NEXT: s_cmp_lg_u32 s2, 0
+; GFX10-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX10-NEXT: ; %bb.6: ; %ComputeEnd
; GFX10-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2
; GFX10-NEXT: ; implicit-def: $vgpr2
-; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo
-; GFX10-NEXT: s_xor_b32 s3, exec_lo, s3
-; GFX10-NEXT: s_cbranch_execz .LBB29_10
-; GFX10-NEXT: ; %bb.9:
-; GFX10-NEXT: v_mov_b32_e32 v2, s2
+; GFX10-NEXT: s_and_saveexec_b32 s2, vcc_lo
+; GFX10-NEXT: s_xor_b32 s2, exec_lo, s2
+; GFX10-NEXT: s_cbranch_execz .LBB29_8
+; GFX10-NEXT: ; %bb.7:
+; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX10-NEXT: .LBB29_10:
+; GFX10-NEXT: .LBB29_8:
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
-; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s3
+; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s2
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX90A-LABEL: local_ds_fadd_one_as:
; GFX90A: ; %bb.0:
+; GFX90A-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX90A-NEXT: s_mov_b64 s[2:3], exec
-; GFX90A-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX90A-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX90A-NEXT: ; implicit-def: $vgpr0
-; GFX90A-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX90A-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX90A-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX90A-NEXT: v_readfirstlane_b32 s7, v1
-; GFX90A-NEXT: v_readlane_b32 s8, v2, s6
-; GFX90A-NEXT: s_mov_b32 m0, s6
-; GFX90A-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX90A-NEXT: v_writelane_b32 v0, s7, m0
-; GFX90A-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX90A-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX90A-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX90A-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX90A-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX90A-NEXT: ; implicit-def: $vgpr2
+; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
+; GFX90A-NEXT: s_add_i32 s5, s5, 4
+; GFX90A-NEXT: ; implicit-def: $vgpr1
+; GFX90A-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX90A-NEXT: s_cbranch_execz .LBB29_2
+; GFX90A-NEXT: ; %bb.1:
+; GFX90A-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX90A-NEXT: s_lshl_b32 s8, s5, 3
+; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX90A-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX90A-NEXT: v_mov_b32_e32 v2, s8
+; GFX90A-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX90A-NEXT: .LBB29_2:
+; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX90A-NEXT: s_mov_b64 s[8:9], exec
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: s_add_i32 s3, s3, 4
-; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX90A-NEXT: v_readfirstlane_b32 s10, v1
+; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX90A-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX90A-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX90A-NEXT: s_cbranch_execz .LBB29_4
; GFX90A-NEXT: ; %bb.3:
-; GFX90A-NEXT: s_lshl_b32 s6, s3, 3
-; GFX90A-NEXT: v_mov_b32_e32 v2, s6
-; GFX90A-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX90A-NEXT: .LBB29_4:
-; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX90A-NEXT: s_mov_b64 s[6:7], exec
-; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
-; GFX90A-NEXT: v_readfirstlane_b32 s8, v2
-; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX90A-NEXT: s_cbranch_execz .LBB29_6
-; GFX90A-NEXT: ; %bb.5:
-; GFX90A-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX90A-NEXT: s_lshl_b32 s3, s3, 4
+; GFX90A-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX90A-NEXT: s_lshl_b32 s2, s5, 4
; GFX90A-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX90A-NEXT: v_mov_b32_e32 v2, s3
+; GFX90A-NEXT: v_mov_b32_e32 v2, s2
; GFX90A-NEXT: ds_add_f32 v2, v1
-; GFX90A-NEXT: .LBB29_6:
-; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX90A-NEXT: s_mov_b64 s[4:5], exec
-; GFX90A-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX90A-NEXT: .LBB29_4:
+; GFX90A-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX90A-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX90A-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX90A-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX90A-NEXT: v_mov_b32_e32 v1, s10
+; GFX90A-NEXT: s_mov_b64 s[2:3], exec
+; GFX90A-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX90A-NEXT: v_bfrev_b32_e32 v1, 1
; GFX90A-NEXT: ; implicit-def: $vgpr0
-; GFX90A-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX90A-NEXT: .LBB29_5: ; %ComputeLoop
; GFX90A-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX90A-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX90A-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX90A-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX90A-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX90A-NEXT: v_readfirstlane_b32 s8, v1
-; GFX90A-NEXT: v_readlane_b32 s9, v2, s3
-; GFX90A-NEXT: s_mov_b32 m0, s3
-; GFX90A-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX90A-NEXT: v_readlane_b32 s9, v2, s5
+; GFX90A-NEXT: s_mov_b32 m0, s5
+; GFX90A-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX90A-NEXT: v_writelane_b32 v0, s8, m0
-; GFX90A-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX90A-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX90A-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX90A-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX90A-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX90A-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX90A-NEXT: ; %bb.6: ; %ComputeEnd
; GFX90A-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX90A-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX90A-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX90A-NEXT: ; implicit-def: $vgpr2
-; GFX90A-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX90A-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX90A-NEXT: s_cbranch_execz .LBB29_10
-; GFX90A-NEXT: ; %bb.9:
-; GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GFX90A-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX90A-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX90A-NEXT: s_cbranch_execz .LBB29_8
+; GFX90A-NEXT: ; %bb.7:
+; GFX90A-NEXT: v_mov_b32_e32 v2, s4
; GFX90A-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX90A-NEXT: .LBB29_10:
-; GFX90A-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX90A-NEXT: .LBB29_8:
+; GFX90A-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX90A-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX90A-NEXT: s_waitcnt lgkmcnt(0)
; GFX90A-NEXT: v_readfirstlane_b32 s2, v2
-; GFX90A-NEXT: v_mov_b32_e32 v1, 0
; GFX90A-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX90A-NEXT: v_mov_b32_e32 v2, s2
+; GFX90A-NEXT: v_mov_b32_e32 v1, 0
+; GFX90A-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX90A-NEXT: global_store_dword v1, v0, s[0:1]
; GFX90A-NEXT: s_endpgm
;
; GFX908-LABEL: local_ds_fadd_one_as:
; GFX908: ; %bb.0:
+; GFX908-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX908-NEXT: s_mov_b64 s[2:3], exec
-; GFX908-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX908-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX908-NEXT: ; implicit-def: $vgpr0
-; GFX908-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX908-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX908-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX908-NEXT: v_readfirstlane_b32 s7, v1
-; GFX908-NEXT: v_readlane_b32 s8, v2, s6
-; GFX908-NEXT: s_mov_b32 m0, s6
-; GFX908-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX908-NEXT: v_writelane_b32 v0, s7, m0
-; GFX908-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX908-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX908-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX908-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX908-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX908-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
-; GFX908-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
-; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
-; GFX908-NEXT: ; implicit-def: $vgpr2
+; GFX908-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX908-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX908-NEXT: s_waitcnt lgkmcnt(0)
+; GFX908-NEXT: s_add_i32 s5, s5, 4
+; GFX908-NEXT: ; implicit-def: $vgpr1
+; GFX908-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX908-NEXT: s_cbranch_execz .LBB29_2
+; GFX908-NEXT: ; %bb.1:
+; GFX908-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX908-NEXT: s_lshl_b32 s8, s5, 3
+; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX908-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX908-NEXT: v_mov_b32_e32 v2, s8
+; GFX908-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX908-NEXT: .LBB29_2:
+; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX908-NEXT: s_mov_b64 s[8:9], exec
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: s_add_i32 s3, s3, 4
-; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX908-NEXT: v_readfirstlane_b32 s10, v1
+; GFX908-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX908-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX908-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX908-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX908-NEXT: s_cbranch_execz .LBB29_4
; GFX908-NEXT: ; %bb.3:
-; GFX908-NEXT: s_lshl_b32 s6, s3, 3
-; GFX908-NEXT: v_mov_b32_e32 v2, s6
-; GFX908-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX908-NEXT: .LBB29_4:
-; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: s_mov_b64 s[6:7], exec
-; GFX908-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX908-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX908-NEXT: s_waitcnt lgkmcnt(0)
-; GFX908-NEXT: v_readfirstlane_b32 s8, v2
-; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX908-NEXT: s_cbranch_execz .LBB29_6
-; GFX908-NEXT: ; %bb.5:
-; GFX908-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX908-NEXT: s_lshl_b32 s3, s3, 4
+; GFX908-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX908-NEXT: s_lshl_b32 s2, s5, 4
; GFX908-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX908-NEXT: v_mov_b32_e32 v2, s3
+; GFX908-NEXT: v_mov_b32_e32 v2, s2
; GFX908-NEXT: ds_add_f32 v2, v1
-; GFX908-NEXT: .LBB29_6:
-; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX908-NEXT: s_mov_b64 s[4:5], exec
-; GFX908-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX908-NEXT: .LBB29_4:
+; GFX908-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX908-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX908-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX908-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX908-NEXT: v_mov_b32_e32 v1, s10
+; GFX908-NEXT: s_mov_b64 s[2:3], exec
+; GFX908-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX908-NEXT: v_bfrev_b32_e32 v1, 1
; GFX908-NEXT: ; implicit-def: $vgpr0
-; GFX908-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX908-NEXT: .LBB29_5: ; %ComputeLoop
; GFX908-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX908-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX908-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX908-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX908-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX908-NEXT: v_readfirstlane_b32 s8, v1
-; GFX908-NEXT: v_readlane_b32 s9, v2, s3
-; GFX908-NEXT: s_mov_b32 m0, s3
-; GFX908-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX908-NEXT: v_readlane_b32 s9, v2, s5
+; GFX908-NEXT: s_mov_b32 m0, s5
+; GFX908-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX908-NEXT: v_writelane_b32 v0, s8, m0
-; GFX908-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX908-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX908-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX908-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX908-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX908-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX908-NEXT: ; %bb.6: ; %ComputeEnd
; GFX908-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX908-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX908-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX908-NEXT: ; implicit-def: $vgpr2
-; GFX908-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX908-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX908-NEXT: s_cbranch_execz .LBB29_10
-; GFX908-NEXT: ; %bb.9:
-; GFX908-NEXT: v_mov_b32_e32 v2, s2
+; GFX908-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX908-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX908-NEXT: s_cbranch_execz .LBB29_8
+; GFX908-NEXT: ; %bb.7:
+; GFX908-NEXT: v_mov_b32_e32 v2, s4
; GFX908-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX908-NEXT: .LBB29_10:
-; GFX908-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX908-NEXT: .LBB29_8:
+; GFX908-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX908-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX908-NEXT: s_waitcnt lgkmcnt(0)
; GFX908-NEXT: v_readfirstlane_b32 s2, v2
-; GFX908-NEXT: v_mov_b32_e32 v1, 0
; GFX908-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX908-NEXT: v_mov_b32_e32 v2, s2
+; GFX908-NEXT: v_mov_b32_e32 v1, 0
+; GFX908-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX908-NEXT: global_store_dword v1, v0, s[0:1]
; GFX908-NEXT: s_endpgm
;
; GFX8-LABEL: local_ds_fadd_one_as:
; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8
; GFX8-NEXT: s_mov_b64 s[2:3], exec
-; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
-; GFX8-NEXT: v_mov_b32_e32 v2, 0x42280000
-; GFX8-NEXT: ; implicit-def: $vgpr0
-; GFX8-NEXT: .LBB29_1: ; %ComputeLoop
-; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT: s_ff1_i32_b64 s6, s[2:3]
-; GFX8-NEXT: s_lshl_b64 s[4:5], 1, s6
-; GFX8-NEXT: v_readfirstlane_b32 s7, v1
-; GFX8-NEXT: v_readlane_b32 s8, v2, s6
-; GFX8-NEXT: s_mov_b32 m0, s6
-; GFX8-NEXT: s_andn2_b64 s[2:3], s[2:3], s[4:5]
-; GFX8-NEXT: v_writelane_b32 v0, s7, m0
-; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
-; GFX8-NEXT: v_add_f32_e32 v1, s8, v1
-; GFX8-NEXT: s_cbranch_scc1 .LBB29_1
-; GFX8-NEXT: ; %bb.2: ; %ComputeEnd
-; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
-; GFX8-NEXT: v_mbcnt_lo_u32_b32 v3, exec_lo, 0
-; GFX8-NEXT: v_mbcnt_hi_u32_b32 v3, exec_hi, v3
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
-; GFX8-NEXT: ; implicit-def: $vgpr2
+; GFX8-NEXT: v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX8-NEXT: v_mbcnt_hi_u32_b32 v0, s3, v0
+; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_add_i32 s5, s5, 4
+; GFX8-NEXT: ; implicit-def: $vgpr1
; GFX8-NEXT: s_mov_b32 m0, -1
+; GFX8-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX8-NEXT: s_cbranch_execz .LBB29_2
+; GFX8-NEXT: ; %bb.1:
+; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX8-NEXT: s_lshl_b32 s8, s5, 3
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX8-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
+; GFX8-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NEXT: ds_add_rtn_f32 v1, v2, v1
+; GFX8-NEXT: .LBB29_2:
+; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX8-NEXT: s_mov_b64 s[8:9], exec
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: s_add_i32 s3, s3, 4
-; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
+; GFX8-NEXT: v_readfirstlane_b32 s10, v1
+; GFX8-NEXT: v_mbcnt_lo_u32_b32 v1, s8, 0
+; GFX8-NEXT: v_mbcnt_hi_u32_b32 v1, s9, v1
+; GFX8-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX8-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
; GFX8-NEXT: s_cbranch_execz .LBB29_4
; GFX8-NEXT: ; %bb.3:
-; GFX8-NEXT: s_lshl_b32 s6, s3, 3
-; GFX8-NEXT: v_mov_b32_e32 v2, s6
-; GFX8-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX8-NEXT: .LBB29_4:
-; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: s_mov_b64 s[6:7], exec
-; GFX8-NEXT: v_mbcnt_lo_u32_b32 v1, s6, 0
-; GFX8-NEXT: v_mbcnt_hi_u32_b32 v1, s7, v1
-; GFX8-NEXT: s_waitcnt lgkmcnt(0)
-; GFX8-NEXT: v_readfirstlane_b32 s8, v2
-; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX8-NEXT: s_cbranch_execz .LBB29_6
-; GFX8-NEXT: ; %bb.5:
-; GFX8-NEXT: s_bcnt1_i32_b64 s6, s[6:7]
-; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, s6
-; GFX8-NEXT: s_lshl_b32 s3, s3, 4
+; GFX8-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v1, s2
+; GFX8-NEXT: s_lshl_b32 s2, s5, 4
; GFX8-NEXT: v_mul_f32_e32 v1, 0x42280000, v1
-; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: ds_add_f32 v2, v1
-; GFX8-NEXT: .LBB29_6:
-; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX8-NEXT: s_mov_b64 s[4:5], exec
-; GFX8-NEXT: v_add_f32_e32 v2, s8, v0
+; GFX8-NEXT: .LBB29_4:
+; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX8-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, 0x42280000, v0
+; GFX8-NEXT: v_add_f32_e32 v0, s10, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, s10
+; GFX8-NEXT: s_mov_b64 s[2:3], exec
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: ; implicit-def: $vgpr0
-; GFX8-NEXT: .LBB29_7: ; %ComputeLoop1
+; GFX8-NEXT: .LBB29_5: ; %ComputeLoop
; GFX8-NEXT: ; =>This Inner Loop Header: Depth=1
-; GFX8-NEXT: s_ff1_i32_b64 s3, s[4:5]
-; GFX8-NEXT: s_lshl_b64 s[6:7], 1, s3
+; GFX8-NEXT: s_ff1_i32_b64 s5, s[2:3]
+; GFX8-NEXT: s_lshl_b64 s[6:7], 1, s5
; GFX8-NEXT: v_readfirstlane_b32 s8, v1
-; GFX8-NEXT: v_readlane_b32 s9, v2, s3
-; GFX8-NEXT: s_mov_b32 m0, s3
-; GFX8-NEXT: s_andn2_b64 s[4:5], s[4:5], s[6:7]
+; GFX8-NEXT: v_readlane_b32 s9, v2, s5
+; GFX8-NEXT: s_mov_b32 m0, s5
+; GFX8-NEXT: s_andn2_b64 s[2:3], s[2:3], s[6:7]
; GFX8-NEXT: v_writelane_b32 v0, s8, m0
-; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
+; GFX8-NEXT: s_cmp_lg_u64 s[2:3], 0
; GFX8-NEXT: v_add_f32_e32 v1, s9, v1
-; GFX8-NEXT: s_cbranch_scc1 .LBB29_7
-; GFX8-NEXT: ; %bb.8: ; %ComputeEnd2
+; GFX8-NEXT: s_cbranch_scc1 .LBB29_5
+; GFX8-NEXT: ; %bb.6: ; %ComputeEnd
; GFX8-NEXT: v_mbcnt_lo_u32_b32 v2, exec_lo, 0
; GFX8-NEXT: v_mbcnt_hi_u32_b32 v2, exec_hi, v2
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; GFX8-NEXT: ; implicit-def: $vgpr2
-; GFX8-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX8-NEXT: s_xor_b64 s[4:5], exec, s[4:5]
-; GFX8-NEXT: s_cbranch_execz .LBB29_10
-; GFX8-NEXT: ; %bb.9:
-; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: s_and_saveexec_b64 s[2:3], vcc
+; GFX8-NEXT: s_xor_b64 s[2:3], exec, s[2:3]
+; GFX8-NEXT: s_cbranch_execz .LBB29_8
+; GFX8-NEXT: ; %bb.7:
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_mov_b32 m0, -1
; GFX8-NEXT: ds_add_rtn_f32 v2, v2, v1
-; GFX8-NEXT: .LBB29_10:
-; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
+; GFX8-NEXT: .LBB29_8:
+; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_readfirstlane_b32 s2, v2
-; GFX8-NEXT: v_add_f32_e32 v2, s2, v0
+; GFX8-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, s2
+; GFX8-NEXT: v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
@@ -8439,153 +8358,186 @@ define amdgpu_kernel void @local_ds_fadd_one_as(ptr addrspace(1) %out, ptr addrs
;
; GFX7-LABEL: local_ds_fadd_one_as:
; GFX7: ; %bb.0:
-; GFX7-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2
-; GFX7-NEXT: s_mov_b32 m0, -1
+; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2
+; GFX7-NEXT: s_mov_b64 s[2:3], exec
+; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
+; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: s_lshl_b32 s4, s3, 3
-; GFX7-NEXT: v_mov_b32_e32 v0, s4
-; GFX7-NEXT: ds_read_b32 v0, v0 offset:32
-; GFX7-NEXT: s_add_i32 s3, s3, 4
-; GFX7-NEXT: s_lshl_b32 s6, s3, 3
-; GFX7-NEXT: s_mov_b64 s[4:5], 0
-; GFX7-NEXT: v_mov_b32_e32 v1, s6
-; GFX7-NEXT: .LBB29_1: ; %atomicrmw.start
+; GFX7-NEXT: s_add_i32 s5, s5, 4
+; GFX7-NEXT: ; implicit-def: $vgpr1
+; GFX7-NEXT: s_mov_b32 m0, -1
+; GFX7-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX7-NEXT: s_cbranch_execz .LBB29_4
+; GFX7-NEXT: ; %bb.1:
+; GFX7-NEXT: s_lshl_b32 s8, s5, 3
+; GFX7-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-NEXT: ds_read_b32 v1, v2
+; GFX7-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v3, s2
+; GFX7-NEXT: v_mul_f32_e32 v3, 0x42280000, v3
+; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: .LBB29_2: ; %atomicrmw.start
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v2, v0
-; GFX7-NEXT: v_add_f32_e32 v0, 0x42280000, v2
-; GFX7-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
+; GFX7-NEXT: v_mov_b32_e32 v4, v1
+; GFX7-NEXT: v_add_f32_e32 v1, v4, v3
+; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v2, v4, v1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
-; GFX7-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX7-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GFX7-NEXT: s_cbranch_execnz .LBB29_1
-; GFX7-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX7-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX7-NEXT: s_mov_b64 s[6:7], exec
-; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s6, 0
-; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s7, v1
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX7-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX7-NEXT: s_cbranch_execz .LBB29_5
-; GFX7-NEXT: ; %bb.3:
-; GFX7-NEXT: s_lshl_b32 s3, s3, 4
-; GFX7-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], v1, v4
+; GFX7-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
+; GFX7-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX7-NEXT: s_cbranch_execnz .LBB29_2
+; GFX7-NEXT: ; %bb.3: ; %Flow18
+; GFX7-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX7-NEXT: .LBB29_4: ; %Flow19
+; GFX7-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX7-NEXT: s_mov_b64 s[8:9], exec
+; GFX7-NEXT: v_readfirstlane_b32 s10, v1
+; GFX7-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s8, 0
+; GFX7-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s9, v1
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX7-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
+; GFX7-NEXT: s_cbranch_execz .LBB29_7
+; GFX7-NEXT: ; %bb.5:
+; GFX7-NEXT: s_lshl_b32 s2, s5, 4
+; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: ds_read_b32 v3, v1
-; GFX7-NEXT: s_bcnt1_i32_b64 s3, s[6:7]
-; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v2, s3
+; GFX7-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
; GFX7-NEXT: v_mul_f32_e32 v2, 0x42280000, v2
-; GFX7-NEXT: s_mov_b64 s[6:7], 0
-; GFX7-NEXT: .LBB29_4: ; %atomicrmw.start2
+; GFX7-NEXT: s_mov_b64 s[8:9], 0
+; GFX7-NEXT: .LBB29_6: ; %atomicrmw.start2
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_add_f32_e32 v4, v3, v2
; GFX7-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
-; GFX7-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
+; GFX7-NEXT: v_cmp_eq_u32_e64 s[2:3], v4, v3
+; GFX7-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
; GFX7-NEXT: v_mov_b32_e32 v3, v4
-; GFX7-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX7-NEXT: s_cbranch_execnz .LBB29_4
-; GFX7-NEXT: .LBB29_5: ; %Flow17
-; GFX7-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX7-NEXT: v_mov_b32_e32 v2, s2
-; GFX7-NEXT: ds_read_b32 v1, v2
+; GFX7-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX7-NEXT: s_cbranch_execnz .LBB29_6
+; GFX7-NEXT: .LBB29_7: ; %Flow17
+; GFX7-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX7-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_mul_f32_e32 v2, 0x42280000, v0
+; GFX7-NEXT: ds_read_b32 v0, v1
+; GFX7-NEXT: v_add_f32_e32 v2, s10, v2
+; GFX7-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX7-NEXT: s_mov_b64 s[2:3], 0
-; GFX7-NEXT: .LBB29_6: ; %atomicrmw.start8
+; GFX7-NEXT: .LBB29_8: ; %atomicrmw.start8
; GFX7-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_mov_b32_e32 v3, v1
-; GFX7-NEXT: v_add_f32_e32 v1, v3, v0
-; GFX7-NEXT: ds_cmpst_rtn_b32 v1, v2, v3, v1
+; GFX7-NEXT: v_mov_b32_e32 v3, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v3, v2
+; GFX7-NEXT: ds_cmpst_rtn_b32 v0, v1, v3, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, v0, v3
; GFX7-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX7-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX7-NEXT: s_cbranch_execnz .LBB29_6
-; GFX7-NEXT: ; %bb.7: ; %atomicrmw.end7
+; GFX7-NEXT: s_cbranch_execnz .LBB29_8
+; GFX7-NEXT: ; %bb.9: ; %atomicrmw.end7
; GFX7-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
-; GFX7-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm
;
; GFX6-LABEL: local_ds_fadd_one_as:
; GFX6: ; %bb.0:
-; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x2
-; GFX6-NEXT: s_mov_b32 m0, -1
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x2
+; GFX6-NEXT: s_mov_b64 s[2:3], exec
+; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v0, s2, 0
+; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v0, s3, v0
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: s_lshl_b32 s4, s3, 3
-; GFX6-NEXT: s_add_i32 s4, s4, 32
-; GFX6-NEXT: v_mov_b32_e32 v0, s4
-; GFX6-NEXT: ds_read_b32 v0, v0
-; GFX6-NEXT: s_add_i32 s3, s3, 4
-; GFX6-NEXT: s_lshl_b32 s6, s3, 3
-; GFX6-NEXT: s_mov_b64 s[4:5], 0
-; GFX6-NEXT: v_mov_b32_e32 v1, s6
-; GFX6-NEXT: .LBB29_1: ; %atomicrmw.start
+; GFX6-NEXT: s_add_i32 s5, s5, 4
+; GFX6-NEXT: ; implicit-def: $vgpr1
+; GFX6-NEXT: s_mov_b32 m0, -1
+; GFX6-NEXT: s_and_saveexec_b64 s[6:7], vcc
+; GFX6-NEXT: s_cbranch_execz .LBB29_4
+; GFX6-NEXT: ; %bb.1:
+; GFX6-NEXT: s_lshl_b32 s8, s5, 3
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: ds_read_b32 v1, v2
+; GFX6-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v3, s2
+; GFX6-NEXT: v_mul_f32_e32 v3, 0x42280000, v3
+; GFX6-NEXT: s_mov_b64 s[8:9], 0
+; GFX6-NEXT: .LBB29_2: ; %atomicrmw.start
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v2, v0
-; GFX6-NEXT: v_add_f32_e32 v0, 0x42280000, v2
-; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v2, v0
+; GFX6-NEXT: v_mov_b32_e32 v4, v1
+; GFX6-NEXT: v_add_f32_e32 v1, v4, v3
+; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v2, v4, v1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v2
-; GFX6-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
-; GFX6-NEXT: s_andn2_b64 exec, exec, s[4:5]
-; GFX6-NEXT: s_cbranch_execnz .LBB29_1
-; GFX6-NEXT: ; %bb.2: ; %atomicrmw.end
-; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: s_mov_b64 s[6:7], exec
-; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s6, 0
-; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s7, v1
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
-; GFX6-NEXT: s_and_saveexec_b64 s[4:5], vcc
-; GFX6-NEXT: s_cbranch_execz .LBB29_5
-; GFX6-NEXT: ; %bb.3:
-; GFX6-NEXT: s_lshl_b32 s3, s3, 4
-; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], v1, v4
+; GFX6-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
+; GFX6-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX6-NEXT: s_cbranch_execnz .LBB29_2
+; GFX6-NEXT: ; %bb.3: ; %Flow16
+; GFX6-NEXT: s_or_b64 exec, exec, s[8:9]
+; GFX6-NEXT: .LBB29_4: ; %Flow17
+; GFX6-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX6-NEXT: s_mov_b64 s[8:9], exec
+; GFX6-NEXT: v_readfirstlane_b32 s10, v1
+; GFX6-NEXT: v_mbcnt_lo_u32_b32_e64 v1, s8, 0
+; GFX6-NEXT: v_mbcnt_hi_u32_b32_e32 v1, s9, v1
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], 0, v1
+; GFX6-NEXT: s_and_saveexec_b64 s[6:7], s[2:3]
+; GFX6-NEXT: s_cbranch_execz .LBB29_7
+; GFX6-NEXT: ; %bb.5:
+; GFX6-NEXT: s_lshl_b32 s2, s5, 4
+; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: ds_read_b32 v3, v1
-; GFX6-NEXT: s_bcnt1_i32_b64 s3, s[6:7]
-; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s3
+; GFX6-NEXT: s_bcnt1_i32_b64 s2, s[8:9]
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v2, s2
; GFX6-NEXT: v_mul_f32_e32 v2, 0x42280000, v2
-; GFX6-NEXT: s_mov_b64 s[6:7], 0
-; GFX6-NEXT: .LBB29_4: ; %atomicrmw.start2
+; GFX6-NEXT: s_mov_b64 s[8:9], 0
+; GFX6-NEXT: .LBB29_6: ; %atomicrmw.start2
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_add_f32_e32 v4, v3, v2
; GFX6-NEXT: ds_cmpst_rtn_b32 v4, v1, v3, v4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v4, v3
-; GFX6-NEXT: s_or_b64 s[6:7], vcc, s[6:7]
+; GFX6-NEXT: v_cmp_eq_u32_e64 s[2:3], v4, v3
+; GFX6-NEXT: s_or_b64 s[8:9], s[2:3], s[8:9]
; GFX6-NEXT: v_mov_b32_e32 v3, v4
-; GFX6-NEXT: s_andn2_b64 exec, exec, s[6:7]
-; GFX6-NEXT: s_cbranch_execnz .LBB29_4
-; GFX6-NEXT: .LBB29_5: ; %Flow15
-; GFX6-NEXT: s_or_b64 exec, exec, s[4:5]
-; GFX6-NEXT: v_mov_b32_e32 v2, s2
-; GFX6-NEXT: ds_read_b32 v1, v2
+; GFX6-NEXT: s_andn2_b64 exec, exec, s[8:9]
+; GFX6-NEXT: s_cbranch_execnz .LBB29_6
+; GFX6-NEXT: .LBB29_7: ; %Flow15
+; GFX6-NEXT: s_or_b64 exec, exec, s[6:7]
+; GFX6-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, s4
+; GFX6-NEXT: v_mul_f32_e32 v2, 0x42280000, v0
+; GFX6-NEXT: ds_read_b32 v0, v1
+; GFX6-NEXT: v_add_f32_e32 v2, s10, v2
+; GFX6-NEXT: v_mov_b32_e32 v3, s10
+; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX6-NEXT: s_mov_b64 s[2:3], 0
-; GFX6-NEXT: .LBB29_6: ; %atomicrmw.start8
+; GFX6-NEXT: .LBB29_8: ; %atomicrmw.start8
; GFX6-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_mov_b32_e32 v3, v1
-; GFX6-NEXT: v_add_f32_e32 v1, v3, v0
-; GFX6-NEXT: ds_cmpst_rtn_b32 v1, v2, v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v3, v0
+; GFX6-NEXT: v_add_f32_e32 v0, v3, v2
+; GFX6-NEXT: ds_cmpst_rtn_b32 v0, v1, v3, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v1, v3
+; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, v0, v3
; GFX6-NEXT: s_or_b64 s[2:3], vcc, s[2:3]
; GFX6-NEXT: s_andn2_b64 exec, exec, s[2:3]
-; GFX6-NEXT: s_cbranch_execnz .LBB29_6
-; GFX6-NEXT: ; %bb.7: ; %atomicrmw.end7
+; GFX6-NEXT: s_cbranch_execnz .LBB29_8
+; GFX6-NEXT: ; %bb.9: ; %atomicrmw.end7
; GFX6-NEXT: s_or_b64 exec, exec, s[2:3]
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
-; GFX6-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
%idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 3
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