[llvm] [AArch64][SVE] Improve code quality of vector unsigned/signed add reductions. (PR #97339)
Dinar Temirbulatov via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 12 03:37:33 PDT 2024
================
@@ -17455,6 +17455,80 @@ static SDValue performVecReduceAddCombineWithUADDLP(SDNode *N,
return DAG.getNode(ISD::VECREDUCE_ADD, DL, MVT::i32, UADDLP);
}
+static SDValue
+performVecReduceAddZextCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
+ const AArch64TargetLowering &TLI) {
+ if (N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND)
+ return SDValue();
+
+ SelectionDAG &DAG = DCI.DAG;
+ auto &Subtarget = DAG.getSubtarget<AArch64Subtarget>();
+ SDNode *ZEXT = N->getOperand(0).getNode();
+ EVT VecVT = ZEXT->getOperand(0).getValueType();
+ SDLoc DL(N);
+
+ SDValue VecOp = ZEXT->getOperand(0);
+ VecVT = VecOp.getValueType();
+ bool IsScalableType = VecVT.isScalableVector();
+ SmallVector<SDValue, 2> ResultValues;
+
+ if (!TLI.isTypeLegal(VecVT)) {
+ SmallVector<SDValue, 2> PrevValues;
+ PrevValues.push_back(VecOp);
+ while (true) {
+
+ if (!VecVT.isScalableVector() &&
+ !PrevValues[0].getValueType().getVectorElementCount().isKnownEven())
+ return SDValue();
+
+ for (SDValue Vec : PrevValues) {
+ SDValue Lo, Hi;
+ std::tie(Lo, Hi) = DAG.SplitVector(Vec, DL);
+ ResultValues.push_back(Lo);
+ ResultValues.push_back(Hi);
+ }
+ if (TLI.isTypeLegal(ResultValues[0].getValueType()))
+ break;
+ PrevValues.clear();
+ std::copy(ResultValues.begin(), ResultValues.end(),
----------------
dtemirbulatov wrote:
Done.
https://github.com/llvm/llvm-project/pull/97339
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