[llvm] 1bad702 - [X86] combineShiftToPMULH - reuse existing SDLoc. NFC.

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2024-07-12T11:35:53+01:00
New Revision: 1bad7024561bc64ed4bfda0772b16376b475eba5

URL: https://github.com/llvm/llvm-project/commit/1bad7024561bc64ed4bfda0772b16376b475eba5
DIFF: https://github.com/llvm/llvm-project/commit/1bad7024561bc64ed4bfda0772b16376b475eba5.diff

LOG: [X86] combineShiftToPMULH - reuse existing SDLoc. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9b3aeb2fd1803..0a11e2134c708 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -47970,10 +47970,10 @@ static SDValue combineMul(SDNode *N, SelectionDAG &DAG,
 // of a MULHU/MULHS. There isn't a way to convey this to the generic DAG
 // combiner.
 static SDValue combineShiftToPMULH(SDNode *N, SelectionDAG &DAG,
+                                   const SDLoc &DL,
                                    const X86Subtarget &Subtarget) {
   assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
            "SRL or SRA node is required here!");
-  SDLoc DL(N);
 
   if (!Subtarget.hasSSE2())
     return SDValue();
@@ -48024,6 +48024,7 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG,
   SDValue N1 = N->getOperand(1);
   ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
   EVT VT = N0.getValueType();
+  SDLoc DL(N);
 
   // Exploits AVX2 VSHLV/VSRLV instructions for efficient unsigned vector shifts
   // with out-of-bounds clamping.
@@ -48039,7 +48040,6 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG,
         ISD::isConstantSplatVector(Cond.getOperand(1).getNode(), SV) &&
         ISD::isConstantSplatVectorAllZeros(N01.getNode()) &&
         SV == VT.getScalarSizeInBits()) {
-      SDLoc DL(N);
       return DAG.getNode(X86ISD::VSHLV, DL, VT, N00, N1);
     }
   }
@@ -48074,10 +48074,8 @@ static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG,
                N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
       MaskOK = Mask.isIntN(N00.getOperand(0).getValueSizeInBits());
     }
-    if (MaskOK && Mask != 0) {
-      SDLoc DL(N);
+    if (MaskOK && Mask != 0)
       return DAG.getNode(ISD::AND, DL, VT, N00, DAG.getConstant(Mask, DL, VT));
-    }
   }
 
   return SDValue();
@@ -48092,7 +48090,7 @@ static SDValue combineShiftRightArithmetic(SDNode *N, SelectionDAG &DAG,
   unsigned Size = VT.getSizeInBits();
   SDLoc DL(N);
 
-  if (SDValue V = combineShiftToPMULH(N, DAG, Subtarget))
+  if (SDValue V = combineShiftToPMULH(N, DAG, DL, Subtarget))
     return V;
 
   // fold sra(x,umin(amt,bw-1)) -> avx2 psrav(x,amt)
@@ -48157,8 +48155,9 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N0.getValueType();
+  SDLoc DL(N);
 
-  if (SDValue V = combineShiftToPMULH(N, DAG, Subtarget))
+  if (SDValue V = combineShiftToPMULH(N, DAG, DL, Subtarget))
     return V;
 
   // Exploits AVX2 VSHLV/VSRLV instructions for efficient unsigned vector shifts
@@ -48175,7 +48174,6 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
         ISD::isConstantSplatVector(Cond.getOperand(1).getNode(), SV) &&
         ISD::isConstantSplatVectorAllZeros(N01.getNode()) &&
         SV == VT.getScalarSizeInBits()) {
-      SDLoc DL(N);
       return DAG.getNode(X86ISD::VSRLV, DL, VT, N00, N1);
     }
   }
@@ -48215,7 +48213,6 @@ static SDValue combineShiftRightLogical(SDNode *N, SelectionDAG &DAG,
   if ((OldMaskSize > 8 && NewMaskSize <= 8) ||
       (OldMaskSize > 32 && NewMaskSize <= 32)) {
     // srl (and X, AndC), ShiftC --> and (srl X, ShiftC), (AndC >> ShiftC)
-    SDLoc DL(N);
     SDValue NewMask = DAG.getConstant(NewMaskVal, DL, VT);
     SDValue NewShift = DAG.getNode(ISD::SRL, DL, VT, N0.getOperand(0), N1);
     return DAG.getNode(ISD::AND, DL, VT, NewShift, NewMask);