[llvm] [AMDGPU] Do not use original PHIs in coercion chains (PR #98063)

[Jay Foad via llvm-commits]

jayfoad wrote:

@jrbyrnes this is generating broken IR in som Vulkan CTS tests. Here's a reduced test case:
```diff
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
index 83016f1d2d3c..d82293c09ef5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-late-codegenprepare.ll
@@ -93,3 +93,22 @@ define amdgpu_kernel void @constant_from_inttoptr() {
   store i8 %load, ptr addrspace(1) undef
   ret void
 }
+
+define void @broken_phi() {
+bb:
+  br label %bb1
+bb1:
+  %i = phi <4 x i8> [ <i8 1, i8 1, i8 1, i8 1>, %bb ], [ %i8, %bb7 ]
+  br i1 false, label %bb3, label %bb2
+bb2:
+  br label %bb3
+bb3:
+  %i4 = phi <4 x i8> [ zeroinitializer, %bb2 ], [ %i, %bb1 ]
+  br i1 false, label %bb7, label %bb5
+bb5:
+  %i6 = call <4 x i8> @llvm.smax.v4i8(<4 x i8> %i4, <4 x i8> zeroinitializer)
+  br label %bb7
+bb7:
+  %i8 = phi <4 x i8> [ zeroinitializer, %bb5 ], [ zeroinitializer, %bb3 ]
+  br label %bb1
+}
```
It fails IR verification with `PHINode should have one entry for each predecessor of its parent basic block!`. Please fix or revert!

@mariusz-sikora-at-amd @dstutt FYI.

https://github.com/llvm/llvm-project/pull/98063