[llvm] 0d9d5f7 - [CodeGen] Guard copy propagation in machine CSE against undefs (#97413)

[via llvm-commits]

Author: Vikram Hegde
Date: 2024-07-12T10:23:35+05:30
New Revision: 0d9d5f7ea282f938e39a9b319076ef84c45ee482

URL: https://github.com/llvm/llvm-project/commit/0d9d5f7ea282f938e39a9b319076ef84c45ee482
DIFF: https://github.com/llvm/llvm-project/commit/0d9d5f7ea282f938e39a9b319076ef84c45ee482.diff

LOG: [CodeGen] Guard copy propagation in machine CSE against undefs (#97413)

Added: 
    llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir

Modified: 
    llvm/lib/CodeGen/MachineCSE.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 4e6101f875589..e39aae56bf116 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -184,7 +184,7 @@ bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
       continue;
     bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
     MachineInstr *DefMI = MRI->getVRegDef(Reg);
-    if (!DefMI->isCopy())
+    if (!DefMI || !DefMI->isCopy())
       continue;
     Register SrcReg = DefMI->getOperand(1).getReg();
     if (!SrcReg.isVirtual())

diff  --git a/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
new file mode 100644
index 0000000000000..1e12a3b22e9a4
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
@@ -0,0 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
+
+# Test to ensure that this does not crash on undefs
+---
+name: copyprop_regsequence_with_undef
+tracksRegLiveness: true
+body:               |
+  bb.0:
+    ; CHECK-LABEL: name: copyprop_regsequence_with_undef
+    ; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %3:sreg_32, %subreg.sub0, [[DEF]], %subreg.sub1
+    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %5:sreg_32, %subreg.sub0, [[DEF1]], %subreg.sub1
+    ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[REG_SEQUENCE]].sub1, [[REG_SEQUENCE1]].sub1, implicit-def $scc
+    %0:sreg_32 = IMPLICIT_DEF
+    %1:sreg_32 = IMPLICIT_DEF
+    %4:sreg_64 = REG_SEQUENCE undef %10:sreg_32, %subreg.sub0, %0:sreg_32, %subreg.sub1
+    %5:sreg_64 = REG_SEQUENCE undef %11:sreg_32, %subreg.sub0, %1:sreg_32, %subreg.sub1
+    %6:sreg_32 = S_ADD_I32 %4.sub1:sreg_64, %5.sub1:sreg_64, implicit-def $scc
+
+...