[llvm] [RISCV]Enable framework to resolve encoding conflicts among vendor-specific CSRs (PR #97287)
Garvit Gupta via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 11 19:26:48 PDT 2024
https://github.com/quic-garvgupt updated https://github.com/llvm/llvm-project/pull/97287
>From 2ab927f092775006f86f6291d5e06acbbc7135f0 Mon Sep 17 00:00:00 2001
From: Garvit Gupta <quic_garvgupt at quicinc.com>
Date: Mon, 1 Jul 2024 04:53:19 -0700
Subject: [PATCH] RISCV]Enable framework to resolve encoding conflicts among
vendor-specific CSRs
This PR is a follow-up of PR #96174 which added the framework to resolve
encoding conflicts among vendor specific CSRs. This PR explicitly
enables this only for the RISCV target.
---
.../Target/RISCV/AsmParser/RISCVAsmParser.cpp | 17 ++++++++++++-----
.../RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 13 ++++++++-----
llvm/lib/Target/RISCV/RISCVSystemOperands.td | 1 +
3 files changed, 21 insertions(+), 10 deletions(-)
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index 333db1b233d1a..a288e7d884d31 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1890,11 +1890,18 @@ ParseStatus RISCVAsmParser::parseCSRSystemRegister(OperandVector &Operands) {
if (CE) {
int64_t Imm = CE->getValue();
if (isUInt<12>(Imm)) {
- auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
- // Accept an immediate representing a named or un-named Sys Reg
- // if the range is valid, regardless of the required features.
- Operands.push_back(
- RISCVOperand::createSysReg(SysReg ? SysReg->Name : "", S, Imm));
+ auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
+ // Accept an immediate representing a named Sys Reg if it satisfies the
+ // the required features.
+ for (auto &Reg : Range) {
+ if (Reg.haveRequiredFeatures(STI->getFeatureBits())) {
+ Operands.push_back(RISCVOperand::createSysReg(Reg.Name, S, Imm));
+ return ParseStatus::Success;
+ }
+ }
+ // Accept an immediate representing an un-named Sys Reg if the range is
+ // valid, regardless of the required features.
+ Operands.push_back(RISCVOperand::createSysReg("", S, Imm));
return ParseStatus::Success;
}
}
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 48b669c78cade..d18ded271a085 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -121,11 +121,14 @@ void RISCVInstPrinter::printCSRSystemRegister(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Imm = MI->getOperand(OpNo).getImm();
- auto SysReg = RISCVSysReg::lookupSysRegByEncoding(Imm);
- if (SysReg && SysReg->haveRequiredFeatures(STI.getFeatureBits()))
- markup(O, Markup::Register) << SysReg->Name;
- else
- markup(O, Markup::Register) << formatImm(Imm);
+ auto Range = RISCVSysReg::lookupSysRegByEncoding(Imm);
+ for (auto &Reg : Range) {
+ if (Reg.haveRequiredFeatures(STI.getFeatureBits())) {
+ markup(O, Markup::Register) << Reg.Name;
+ return;
+ }
+ }
+ markup(O, Markup::Register) << formatImm(Imm);
}
void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index db840b3027492..a836227e18957 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -49,6 +49,7 @@ def SysRegsList : GenericTable {
let PrimaryKey = [ "Encoding" ];
let PrimaryKeyName = "lookupSysRegByEncoding";
+ let PrimaryKeyReturnRange = true;
}
def lookupSysRegByName : SearchIndex {
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