[llvm] [CodeGen] Guard copy propagation in machine CSE against undefs (PR #97413)
Vikram Hegde via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 11 08:18:46 PDT 2024
https://github.com/vikramRH updated https://github.com/llvm/llvm-project/pull/97413
>From b8fbb24f89d23daf805daf7f4be57334f19cd8f2 Mon Sep 17 00:00:00 2001
From: Vikram <Vikram.Hegde at amd.com>
Date: Tue, 2 Jul 2024 08:47:00 -0400
Subject: [PATCH 1/4] [CodeGen][NFC] Guard copy propogation in machine CSE
against undefs
---
llvm/lib/CodeGen/MachineCSE.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp
index 4e6101f875589..e39aae56bf116 100644
--- a/llvm/lib/CodeGen/MachineCSE.cpp
+++ b/llvm/lib/CodeGen/MachineCSE.cpp
@@ -184,7 +184,7 @@ bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
continue;
bool OnlyOneUse = MRI->hasOneNonDBGUse(Reg);
MachineInstr *DefMI = MRI->getVRegDef(Reg);
- if (!DefMI->isCopy())
+ if (!DefMI || !DefMI->isCopy())
continue;
Register SrcReg = DefMI->getOperand(1).getReg();
if (!SrcReg.isVirtual())
>From 83d165807d910a475d601317ce512fb1826752b5 Mon Sep 17 00:00:00 2001
From: Vikram <Vikram.Hegde at amd.com>
Date: Thu, 4 Jul 2024 14:07:26 -0400
Subject: [PATCH 2/4] add test
---
.../CodeGen/AMDGPU/machine-cse-copyprop.mir | 21 +++++++++++++++++++
1 file changed, 21 insertions(+)
create mode 100644 llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
diff --git a/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir b/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
new file mode 100644
index 0000000000000..ab759657d5d7a
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
@@ -0,0 +1,21 @@
+# RUN: llc -mtriple=amdgcn -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
+
+# Test to ensure that this does not crash on undefs
+# CHECK-LABEL: name: machine-cse-copyprop
+# CHECK: IMPLICIT_DEF
+# CHECK-NOT: COPY
+# CHECK: S_ADD_I32
+---
+name: machine-cse-copyprop
+tracksRegLiveness: true
+body: |
+ bb.0:
+ %0:sreg_32 = IMPLICIT_DEF
+ %1:sreg_32 = IMPLICIT_DEF
+ %2:sreg_32 = COPY %0
+ %3:sreg_32 = COPY %1
+ %4:sreg_64 = REG_SEQUENCE undef %10:sreg_32, %subreg.sub0, %2:sreg_32, %subreg.sub1
+ %5:sreg_64 = REG_SEQUENCE undef %11:sreg_32, %subreg.sub0, %3:sreg_32, %subreg.sub1
+ %6:sreg_32 = S_ADD_I32 %4.sub1:sreg_64, %5.sub1:sreg_64, implicit-def $scc
+
+...
>From 58320622a4f8373a9f91e4fb5e41579a6e7300d3 Mon Sep 17 00:00:00 2001
From: Vikram <Vikram.Hegde at amd.com>
Date: Mon, 8 Jul 2024 02:27:03 -0400
Subject: [PATCH 3/4] review comments
---
.../CodeGen/AMDGPU/machine-cse-copyprop.mir | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir b/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
index ab759657d5d7a..7d644b0b19582 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
+++ b/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
@@ -1,21 +1,22 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -run-pass=machine-cse -verify-machineinstrs -o - %s | FileCheck %s
# Test to ensure that this does not crash on undefs
-# CHECK-LABEL: name: machine-cse-copyprop
-# CHECK: IMPLICIT_DEF
-# CHECK-NOT: COPY
-# CHECK: S_ADD_I32
---
name: machine-cse-copyprop
tracksRegLiveness: true
body: |
bb.0:
+ ; CHECK-LABEL: name: machine-cse-copyprop
+ ; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %3:sreg_32, %subreg.sub0, [[DEF]], %subreg.sub1
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %5:sreg_32, %subreg.sub0, [[DEF1]], %subreg.sub1
+ ; CHECK-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[REG_SEQUENCE]].sub1, [[REG_SEQUENCE1]].sub1, implicit-def $scc
%0:sreg_32 = IMPLICIT_DEF
%1:sreg_32 = IMPLICIT_DEF
- %2:sreg_32 = COPY %0
- %3:sreg_32 = COPY %1
- %4:sreg_64 = REG_SEQUENCE undef %10:sreg_32, %subreg.sub0, %2:sreg_32, %subreg.sub1
- %5:sreg_64 = REG_SEQUENCE undef %11:sreg_32, %subreg.sub0, %3:sreg_32, %subreg.sub1
+ %4:sreg_64 = REG_SEQUENCE undef %10:sreg_32, %subreg.sub0, %0:sreg_32, %subreg.sub1
+ %5:sreg_64 = REG_SEQUENCE undef %11:sreg_32, %subreg.sub0, %1:sreg_32, %subreg.sub1
%6:sreg_32 = S_ADD_I32 %4.sub1:sreg_64, %5.sub1:sreg_64, implicit-def $scc
...
>From 08bdad3e3d1c83636e8f884178616b528bd58564 Mon Sep 17 00:00:00 2001
From: Vikram <Vikram.Hegde at amd.com>
Date: Thu, 11 Jul 2024 10:22:29 -0400
Subject: [PATCH 4/4] review comment
---
...e-cse-copyprop.mir => copyprop_regsequence_with_undef.mir} | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
rename llvm/test/CodeGen/AMDGPU/{machine-cse-copyprop.mir => copyprop_regsequence_with_undef.mir} (92%)
diff --git a/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
similarity index 92%
rename from llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
rename to llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
index 7d644b0b19582..1e12a3b22e9a4 100644
--- a/llvm/test/CodeGen/AMDGPU/machine-cse-copyprop.mir
+++ b/llvm/test/CodeGen/AMDGPU/copyprop_regsequence_with_undef.mir
@@ -3,11 +3,11 @@
# Test to ensure that this does not crash on undefs
---
-name: machine-cse-copyprop
+name: copyprop_regsequence_with_undef
tracksRegLiveness: true
body: |
bb.0:
- ; CHECK-LABEL: name: machine-cse-copyprop
+ ; CHECK-LABEL: name: copyprop_regsequence_with_undef
; CHECK: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE undef %3:sreg_32, %subreg.sub0, [[DEF]], %subreg.sub1
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