[llvm] [LLVM] Factor disabled Libcalls into the initializer (PR #98421)
Joseph Huber via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 11 03:52:55 PDT 2024
https://github.com/jhuber6 updated https://github.com/llvm/llvm-project/pull/98421
>From 6936f1a2c708c1b30f4181f2c25aba2e441a8230 Mon Sep 17 00:00:00 2001
From: Joseph Huber <huberjn at outlook.com>
Date: Wed, 10 Jul 2024 19:13:43 -0500
Subject: [PATCH] [LLVM] Factor disabled Libcalls into the initializer
Summary:
These Libcalls represent which functions are available to the backend.
If a runtime call is not available, the target sets the the name to
`nullptr`. Currently, this logic is spread around the various targets.
This patch pulls all of the locations that disable libcalls into the
intializer.
The motivation behind this patch is that currently the LTO handling uses
the list of all runtime calls to determine which functions cannot be
internalized and must be extracted from static libraries. We do not want
this to happen for libcalls that are not emitted by the backend. A
follow-up patch will move out this logic so the LTO pass can know which
rtlib calls are actually used by the backend.
---
llvm/lib/CodeGen/TargetLoweringBase.cpp | 134 ++++++++++++++++++
.../Target/AArch64/AArch64ISelLowering.cpp | 6 -
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 6 -
llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 --
llvm/lib/Target/AVR/AVRISelLowering.cpp | 16 ---
.../Target/Hexagon/HexagonISelLowering.cpp | 5 -
.../LoongArch/LoongArchISelLowering.cpp | 8 --
llvm/lib/Target/Mips/MipsISelLowering.cpp | 10 --
llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 10 --
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 -
llvm/lib/Target/Sparc/SparcISelLowering.cpp | 11 --
.../Target/SystemZ/SystemZISelLowering.cpp | 3 -
llvm/lib/Target/X86/X86ISelLowering.cpp | 18 ---
13 files changed, 134 insertions(+), 112 deletions(-)
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 353b0cafbd72e..02c08294bae7f 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -290,6 +290,140 @@ void TargetLoweringBase::InitLibcalls(const Triple &TT) {
setLibcallName(RTLIB::FREXP_F128, nullptr);
setLibcallName(RTLIB::FREXP_PPCF128, nullptr);
}
+
+ // Disable most libcalls on AMDGPU.
+ if (TT.isAMDGPU()) {
+ for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
+ if (I < RTLIB::ATOMIC_LOAD || I > RTLIB::ATOMIC_FETCH_NAND_16)
+ setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
+ }
+ }
+
+ if (TT.isLoongArch()) {
+ if (!TT.isLoongArch64()) {
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ }
+
+ // The MULO libcall is not part of libgcc, only compiler-rt.
+ setLibcallName(RTLIB::MULO_I128, nullptr);
+ }
+
+ if (TT.isAArch64() && TT.isOSMSVCRT()) {
+ // MSVCRT doesn't have powi; fall back to pow
+ setLibcallName(RTLIB::POWI_F32, nullptr);
+ setLibcallName(RTLIB::POWI_F64, nullptr);
+ }
+
+ if (TT.isARM() || TT.isThumb()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ setLibcallName(RTLIB::MULO_I128, nullptr);
+
+ if (TT.isOSMSVCRT()) {
+ // MSVCRT doesn't have powi; fall back to pow
+ setLibcallName(RTLIB::POWI_F32, nullptr);
+ setLibcallName(RTLIB::POWI_F64, nullptr);
+ }
+ }
+
+ if (TT.getArch() == Triple::ArchType::avr) {
+ // Division rtlib functions (not supported), use divmod functions instead
+ setLibcallName(RTLIB::SDIV_I8, nullptr);
+ setLibcallName(RTLIB::SDIV_I16, nullptr);
+ setLibcallName(RTLIB::SDIV_I32, nullptr);
+ setLibcallName(RTLIB::UDIV_I8, nullptr);
+ setLibcallName(RTLIB::UDIV_I16, nullptr);
+ setLibcallName(RTLIB::UDIV_I32, nullptr);
+
+ // Modulus rtlib functions (not supported), use divmod functions instead
+ setLibcallName(RTLIB::SREM_I8, nullptr);
+ setLibcallName(RTLIB::SREM_I16, nullptr);
+ setLibcallName(RTLIB::SREM_I32, nullptr);
+ setLibcallName(RTLIB::UREM_I8, nullptr);
+ setLibcallName(RTLIB::UREM_I16, nullptr);
+ setLibcallName(RTLIB::UREM_I32, nullptr);
+ }
+
+ if (TT.getArch() == Triple::ArchType::hexagon) {
+ // These cause problems when the shift amount is non-constant.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ }
+
+ if (TT.isMIPS()) {
+ if (!TT.isMIPS64()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ }
+ setLibcallName(RTLIB::MULO_I128, nullptr);
+ }
+
+ if (TT.isPPC()) {
+ if (!TT.isPPC64()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ }
+ setLibcallName(RTLIB::MULO_I128, nullptr);
+ }
+
+ if (TT.isSPARC()) {
+ if (!TT.isSPARC64()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ }
+ setLibcallName(RTLIB::MULO_I128, nullptr);
+ }
+
+ if (!TT.isRISCV64()) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ }
+
+ if (TT.isX86()) {
+ if (TT.getArch() == Triple::ArchType::x86) {
+ // These libcalls are not available in 32-bit.
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ setLibcallName(RTLIB::MUL_I128, nullptr);
+ setLibcallName(RTLIB::MULO_I64, nullptr);
+ }
+ setLibcallName(RTLIB::MULO_I128, nullptr);
+
+ if (TT.isOSMSVCRT()) {
+ // MSVCRT doesn't have powi; fall back to pow
+ setLibcallName(RTLIB::POWI_F32, nullptr);
+ setLibcallName(RTLIB::POWI_F64, nullptr);
+ }
+ }
+
+ if (TT.isSystemZ()) {
+ setLibcallName(RTLIB::SRL_I128, nullptr);
+ setLibcallName(RTLIB::SHL_I128, nullptr);
+ setLibcallName(RTLIB::SRA_I128, nullptr);
+ }
}
/// GetFPLibCall - Helper to return the right libcall for the given floating
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e5d5c6b6832af..359a3d194f04e 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1010,12 +1010,6 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
}
- if (Subtarget->getTargetTriple().isOSMSVCRT()) {
- // MSVCRT doesn't have powi; fall back to pow
- setLibcallName(RTLIB::POWI_F32, nullptr);
- setLibcallName(RTLIB::POWI_F64, nullptr);
- }
-
// Make floating-point constants legal for the large code model, so they don't
// become loads from the constant pool.
if (Subtarget->isTargetMachO() && TM.getCodeModel() == CodeModel::Large) {
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index ef30bf6d993fa..26426575aeed3 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -574,12 +574,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SELECT, MVT::v12f32, Promote);
AddPromotedToType(ISD::SELECT, MVT::v12f32, MVT::v12i32);
- // Disable most libcalls.
- for (int I = 0; I < RTLIB::UNKNOWN_LIBCALL; ++I) {
- if (I < RTLIB::ATOMIC_LOAD || I > RTLIB::ATOMIC_FETCH_NAND_16)
- setLibcallName(static_cast<RTLIB::Libcall>(I), nullptr);
- }
-
setSchedulingPreference(Sched::RegPressure);
setJumpIsExpensive(true);
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cc36e8b33472b..4589d01b856b6 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -581,14 +581,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
}
}
- // These libcalls are not available in 32-bit.
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
- setLibcallName(RTLIB::MUL_I128, nullptr);
- setLibcallName(RTLIB::MULO_I64, nullptr);
- setLibcallName(RTLIB::MULO_I128, nullptr);
-
// RTLIB
if (Subtarget->isAAPCS_ABI() &&
(Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
@@ -1309,12 +1301,6 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
}
- if (Subtarget->getTargetTriple().isOSMSVCRT()) {
- // MSVCRT doesn't have powi; fall back to pow
- setLibcallName(RTLIB::POWI_F32, nullptr);
- setLibcallName(RTLIB::POWI_F64, nullptr);
- }
-
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
diff --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 8346b1c119ee9..0046e757f4efa 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -199,22 +199,6 @@ AVRTargetLowering::AVRTargetLowering(const AVRTargetMachine &TM,
// improvements in how we treat 16-bit "registers" to be feasible.
}
- // Division rtlib functions (not supported), use divmod functions instead
- setLibcallName(RTLIB::SDIV_I8, nullptr);
- setLibcallName(RTLIB::SDIV_I16, nullptr);
- setLibcallName(RTLIB::SDIV_I32, nullptr);
- setLibcallName(RTLIB::UDIV_I8, nullptr);
- setLibcallName(RTLIB::UDIV_I16, nullptr);
- setLibcallName(RTLIB::UDIV_I32, nullptr);
-
- // Modulus rtlib functions (not supported), use divmod functions instead
- setLibcallName(RTLIB::SREM_I8, nullptr);
- setLibcallName(RTLIB::SREM_I16, nullptr);
- setLibcallName(RTLIB::SREM_I32, nullptr);
- setLibcallName(RTLIB::UREM_I8, nullptr);
- setLibcallName(RTLIB::UREM_I16, nullptr);
- setLibcallName(RTLIB::UREM_I32, nullptr);
-
// Division and modulus rtlib functions
setLibcallName(RTLIB::SDIVREM_I8, "__divmodqi4");
setLibcallName(RTLIB::SDIVREM_I16, "__divmodhi4");
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index aefd94e69b0e1..09fe5264e0955 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1901,11 +1901,6 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setLibcallName(RTLIB::FPROUND_F32_F16, "__truncsfhf2");
setLibcallName(RTLIB::FPROUND_F64_F16, "__truncdfhf2");
setLibcallName(RTLIB::FPEXT_F16_F32, "__extendhfsf2");
-
- // These cause problems when the shift amount is non-constant.
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
}
const char* HexagonTargetLowering::getTargetNodeName(unsigned Opcode) const {
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 521239f5e3193..5c4fddd5116ea 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -152,16 +152,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_VOID, MVT::i64, Custom);
setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
-
- // Set libcalls.
- setLibcallName(RTLIB::MUL_I128, nullptr);
- // The MULO libcall is not part of libgcc, only compiler-rt.
- setLibcallName(RTLIB::MULO_I64, nullptr);
}
- // The MULO libcall is not part of libgcc, only compiler-rt.
- setLibcallName(RTLIB::MULO_I128, nullptr);
-
setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
static const ISD::CondCode FPCCToExpand[] = {
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 973ac0e79cbcc..7d8adb9a00311 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -517,16 +517,6 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setTargetDAGCombine({ISD::SDIVREM, ISD::UDIVREM, ISD::SELECT, ISD::AND,
ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL});
- if (ABI.IsO32()) {
- // These libcalls are not available in 32-bit.
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
- setLibcallName(RTLIB::MUL_I128, nullptr);
- setLibcallName(RTLIB::MULO_I64, nullptr);
- setLibcallName(RTLIB::MULO_I128, nullptr);
- }
-
if (Subtarget.isGP64bit())
setMaxAtomicSizeInBitsSupported(64);
else
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 4d4008ac0ba70..6aabf5cd8c594 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1377,16 +1377,6 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
}
- setLibcallName(RTLIB::MULO_I128, nullptr);
- if (!isPPC64) {
- // These libcalls are not available in 32-bit.
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
- setLibcallName(RTLIB::MUL_I128, nullptr);
- setLibcallName(RTLIB::MULO_I64, nullptr);
- }
-
if (shouldInlineQuadwordAtomics())
setMaxAtomicSizeInBitsSupported(128);
else if (isPPC64)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 19f958ccfd2e1..b6f3afb9bd534 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -295,11 +295,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
}
}
setOperationAction(ISD::SADDO, MVT::i32, Custom);
- } else {
- setLibcallName(
- {RTLIB::SHL_I128, RTLIB::SRL_I128, RTLIB::SRA_I128, RTLIB::MUL_I128},
- nullptr);
- setLibcallName(RTLIB::MULO_I64, nullptr);
}
if (!Subtarget.hasStdExtZmmul()) {
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 13184a1eb0b10..42ba70367fcb1 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1793,17 +1793,6 @@ SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Custom);
}
- if (!Subtarget->is64Bit()) {
- // These libcalls are not available in 32-bit.
- setLibcallName(RTLIB::MULO_I64, nullptr);
- setLibcallName(RTLIB::MUL_I128, nullptr);
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
- }
-
- setLibcallName(RTLIB::MULO_I128, nullptr);
-
if (!Subtarget->isV9()) {
// SparcV8 does not have FNEGD and FABSD.
setOperationAction(ISD::FNEG, MVT::f64, Custom);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index be6503f4ddac7..dd88cd1bcc7fc 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -345,9 +345,6 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
// Also expand 256 bit shifts if i128 is a legal type.
if (isTypeLegal(MVT::i128)) {
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e116285d043c0..65eb5577757a7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -180,12 +180,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
}
}
- if (Subtarget.getTargetTriple().isOSMSVCRT()) {
- // MSVCRT doesn't have powi; fall back to pow
- setLibcallName(RTLIB::POWI_F32, nullptr);
- setLibcallName(RTLIB::POWI_F64, nullptr);
- }
-
if (Subtarget.canUseCMPXCHG16B())
setMaxAtomicSizeInBitsSupported(128);
else if (Subtarget.canUseCMPXCHG8B())
@@ -2444,18 +2438,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::SSUBO_CARRY, VT, Custom);
}
- if (!Subtarget.is64Bit()) {
- // These libcalls are not available in 32-bit.
- setLibcallName(RTLIB::SHL_I128, nullptr);
- setLibcallName(RTLIB::SRL_I128, nullptr);
- setLibcallName(RTLIB::SRA_I128, nullptr);
- setLibcallName(RTLIB::MUL_I128, nullptr);
- // The MULO libcall is not part of libgcc, only compiler-rt.
- setLibcallName(RTLIB::MULO_I64, nullptr);
- }
- // The MULO libcall is not part of libgcc, only compiler-rt.
- setLibcallName(RTLIB::MULO_I128, nullptr);
-
// Combine sin / cos into _sincos_stret if it is available.
if (getLibcallName(RTLIB::SINCOS_STRET_F32) != nullptr &&
getLibcallName(RTLIB::SINCOS_STRET_F64) != nullptr) {
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