[llvm] [AArch64] Improve the codegen for sdiv 2 (PR #98324)

[Yingwei Zheng via llvm-commits]

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@@ -202,9 +202,8 @@ define <4 x i32> @test_bit_sink_operand(<4 x i32> %src, <4 x i32> %dst, <4 x i32
 ; CHECK-SD:       // %bb.0: // %entry
 ; CHECK-SD-NEXT:    sub sp, sp, #32
 ; CHECK-SD-NEXT:    .cfi_def_cfa_offset 32
-; CHECK-SD-NEXT:    cmp w0, #0
+; CHECK-SD-NEXT:    add w8, w0, w0, lsr #31
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dtcxzyw wrote:

It would be better to fold `X < 0 ? X : X + 1` into `X + (X >>31)` on AArch64 backend (as we already did on RISC-V).



https://github.com/llvm/llvm-project/pull/98324