[llvm] [GISel] Make create.*InstructionSelector arguments const (PR #98243)
Michael Maitland via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 10 06:01:25 PDT 2024
https://github.com/michaelmaitland updated https://github.com/llvm/llvm-project/pull/98243
>From 6a2766ee621669e7329898facf4523b3d2719b05 Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 9 Jul 2024 16:11:18 -0700
Subject: [PATCH 1/2] [GISel] Make create.*InstructionSelector arguments const
The InstructionSelector takes `const` arguments.
---
.../Target/AArch64/GISel/AArch64InstructionSelector.cpp | 4 ++--
llvm/lib/Target/Mips/MipsInstructionSelector.cpp | 7 ++++---
llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp | 4 ++--
llvm/lib/Target/RISCV/RISCV.h | 7 ++++---
llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp | 4 ++--
5 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 9e0860934f777..1ff8a7e32a156 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -7790,8 +7790,8 @@ void AArch64InstructionSelector::processPHIs(MachineFunction &MF) {
namespace llvm {
InstructionSelector *
createAArch64InstructionSelector(const AArch64TargetMachine &TM,
- AArch64Subtarget &Subtarget,
- AArch64RegisterBankInfo &RBI) {
+ const AArch64Subtarget &Subtarget,
+ const AArch64RegisterBankInfo &RBI) {
return new AArch64InstructionSelector(TM, Subtarget, RBI);
}
}
diff --git a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
index 4e1e27088cce4..332749165a3ff 100644
--- a/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
+++ b/llvm/lib/Target/Mips/MipsInstructionSelector.cpp
@@ -927,9 +927,10 @@ bool MipsInstructionSelector::select(MachineInstr &I) {
}
namespace llvm {
-InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &TM,
- MipsSubtarget &Subtarget,
- MipsRegisterBankInfo &RBI) {
+InstructionSelector *
+createMipsInstructionSelector(const MipsTargetMachine &TM,
+ const MipsSubtarget &Subtarget,
+ const MipsRegisterBankInfo &RBI) {
return new MipsInstructionSelector(TM, Subtarget, RBI);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
index f511a20109803..fdb1ebace0010 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
@@ -1330,8 +1330,8 @@ void RISCVInstructionSelector::emitFence(AtomicOrdering FenceOrdering,
namespace llvm {
InstructionSelector *
createRISCVInstructionSelector(const RISCVTargetMachine &TM,
- RISCVSubtarget &Subtarget,
- RISCVRegisterBankInfo &RBI) {
+ const RISCVSubtarget &Subtarget,
+ const RISCVRegisterBankInfo &RBI) {
return new RISCVInstructionSelector(TM, Subtarget, RBI);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 8d2e1fc340c3e..27a432b818312 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -79,9 +79,10 @@ void initializeRISCVMoveMergePass(PassRegistry &);
FunctionPass *createRISCVPushPopOptimizationPass();
void initializeRISCVPushPopOptPass(PassRegistry &);
-InstructionSelector *createRISCVInstructionSelector(const RISCVTargetMachine &,
- RISCVSubtarget &,
- RISCVRegisterBankInfo &);
+InstructionSelector *
+createRISCVInstructionSelector(const RISCVTargetMachine &,
+ const RISCVSubtarget &,
+ const RISCVRegisterBankInfo &);
void initializeRISCVDAGToDAGISelLegacyPass(PassRegistry &);
FunctionPass *createRISCVPostLegalizerCombiner();
diff --git a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
index d73873812eeb6..2fb499122fbbf 100644
--- a/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
@@ -1871,7 +1871,7 @@ bool X86InstructionSelector::selectSelect(MachineInstr &I,
InstructionSelector *
llvm::createX86InstructionSelector(const X86TargetMachine &TM,
- X86Subtarget &Subtarget,
- X86RegisterBankInfo &RBI) {
+ const X86Subtarget &Subtarget,
+ const X86RegisterBankInfo &RBI) {
return new X86InstructionSelector(TM, Subtarget, RBI);
}
>From c31b59d8af6e71844fada30ec5233837277d938e Mon Sep 17 00:00:00 2001
From: Michael Maitland <michaeltmaitland at gmail.com>
Date: Tue, 9 Jul 2024 16:30:25 -0700
Subject: [PATCH 2/2] fixup! add to header files
---
llvm/lib/Target/AArch64/AArch64.h | 3 ++-
llvm/lib/Target/Mips/Mips.h | 6 +++---
llvm/lib/Target/X86/X86.h | 4 ++--
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64.h b/llvm/lib/Target/AArch64/AArch64.h
index 66ad701d83958..ff19327c69202 100644
--- a/llvm/lib/Target/AArch64/AArch64.h
+++ b/llvm/lib/Target/AArch64/AArch64.h
@@ -62,7 +62,8 @@ FunctionPass *createSMEABIPass();
ModulePass *createSVEIntrinsicOptsPass();
InstructionSelector *
createAArch64InstructionSelector(const AArch64TargetMachine &,
- AArch64Subtarget &, AArch64RegisterBankInfo &);
+ const AArch64Subtarget &,
+ const AArch64RegisterBankInfo &);
FunctionPass *createAArch64O0PreLegalizerCombiner();
FunctionPass *createAArch64PreLegalizerCombiner();
FunctionPass *createAArch64PostLegalizerCombiner(bool IsOptNone);
diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h
index 36a17334ae3b9..e3e9e17191670 100644
--- a/llvm/lib/Target/Mips/Mips.h
+++ b/llvm/lib/Target/Mips/Mips.h
@@ -41,9 +41,9 @@ FunctionPass *createMipsPreLegalizeCombiner();
FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone);
FunctionPass *createMipsMulMulBugPass();
-InstructionSelector *createMipsInstructionSelector(const MipsTargetMachine &,
- MipsSubtarget &,
- MipsRegisterBankInfo &);
+InstructionSelector *
+createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &,
+ const MipsRegisterBankInfo &);
void initializeMicroMipsSizeReducePass(PassRegistry &);
void initializeMipsBranchExpansionPass(PassRegistry &);
diff --git a/llvm/lib/Target/X86/X86.h b/llvm/lib/Target/X86/X86.h
index d6e0d5e3a3b2c..3d7a322d392f7 100644
--- a/llvm/lib/Target/X86/X86.h
+++ b/llvm/lib/Target/X86/X86.h
@@ -161,8 +161,8 @@ FunctionPass *createX86InsertX87waitPass();
FunctionPass *createX86PartialReductionPass();
InstructionSelector *createX86InstructionSelector(const X86TargetMachine &TM,
- X86Subtarget &,
- X86RegisterBankInfo &);
+ const X86Subtarget &,
+ const X86RegisterBankInfo &);
FunctionPass *createX86LoadValueInjectionLoadHardeningPass();
FunctionPass *createX86LoadValueInjectionRetHardeningPass();
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